diff --git a/.cargo/config b/.cargo/config index 0f05304..956cc38 100644 --- a/.cargo/config +++ b/.cargo/config @@ -1,2 +1,2 @@ [target.'cfg(unix)'] -runner = "sudo" +runner = "sudo -E" diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..1d3355c --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "leechcore-sys/src/leechcore"] + path = leechcore-sys/src/leechcore + url = https://github.com/ufrisk/LeechCore diff --git a/Cargo.toml b/Cargo.toml index 07cd23a..8de5549 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,34 +1,9 @@ -[package] -name = "memflow-pcileech" -version = "0.1.0" -authors = ["ko1N "] -edition = "2018" -description = "pcileech fpga connector for the memflow physical memory introspection framework" -homepage = "https://github.com/memflow/memflow-pcileech" -repository = "https://github.com/memflow/memflow-pcileech" -readme = "README.md" - -[lib] -crate-type = ["lib", "cdylib"] - -[dependencies] -memflow = { version = "0.1", features = ["inventory"] } -memflow-derive = "0.1" -log = { version = "0.4.8", default-features = false } -rusb = "0.6.0" -dataview = "0.1" -pretty-hex = "0.1" -c2rust-bitfields = "0.3.0" -libc = "0.2" - -[dev-dependencies] -clap = "2.33.0" -simple_logger = "1.0.1" - -[features] -default = [] -plugin = [] - -[[example]] -name = "read_pcileech" -path = "examples/read_pcileech.rs" +[workspace] +members = [ + "leechcore-sys", + "memflow-pcileech", +] +default-members = [ + "leechcore-sys", + "memflow-pcileech", +] diff --git a/LICENSE b/LICENSE index 425e0e2..9cecc1d 100644 --- a/LICENSE +++ b/LICENSE @@ -1,21 +1,674 @@ -MIT License - -Copyright (c) 2020 ko1N - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 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If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + {project} Copyright (C) {year} {fullname} + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/c-shell b/c-shell deleted file mode 100644 index 522eaae..0000000 --- a/c-shell +++ /dev/null @@ -1,168 +0,0 @@ -// Example program -#include -#include -#include - -#define WORD uint16_t -#define DWORD uint32_t -#define BYTE uint8_t -#define PBYTE uint8_t* -#define TRUE 1 -#define BOOL int -#define QWORD uint64_t -#define FALSE 0 -#define PDWORD DWORD* - -#define ENDIAN_SWAP_DWORD(x) (x = (x << 24) | ((x >> 8) & 0xff00) | ((x << 8) & 0xff0000) | (x >> 24)) - -#define TLP_MRd32 0x00 -#define TLP_MRd64 0x20 -#define TLP_MRdLk32 0x01 -#define TLP_MRdLk64 0x21 -#define TLP_MWr32 0x40 -#define TLP_MWr64 0x60 -#define TLP_IORd 0x02 -#define TLP_IOWr 0x42 -#define TLP_CfgRd0 0x04 -#define TLP_CfgRd1 0x05 -#define TLP_CfgWr0 0x44 -#define TLP_CfgWr1 0x45 -#define TLP_Cpl 0x0A -#define TLP_CplD 0x4A -#define TLP_CplLk 0x0B -#define TLP_CplDLk 0x4B - -#define MAX_SIZE_TX 0x3f0 - -typedef struct tdTLP_HDR { - WORD Length : 10; - WORD _AT : 2; - WORD _Attr : 2; - WORD _EP : 1; - WORD _TD : 1; - BYTE _R1 : 4; - BYTE _TC : 3; - BYTE _R2 : 1; - BYTE TypeFmt; -} TLP_HDR, *PTLP_HDR; - -typedef struct tdTLP_HDR_MRdWr32 { - TLP_HDR h; - BYTE FirstBE : 4; - BYTE LastBE : 4; - BYTE Tag; - WORD RequesterID; - DWORD Address; -} TLP_HDR_MRdWr32, *PTLP_HDR_MRdWr32; - -typedef struct tdTLP_HDR_MRdWr64 { - TLP_HDR h; - BYTE FirstBE : 4; - BYTE LastBE : 4; - BYTE Tag; - WORD RequesterID; - DWORD AddressHigh; - DWORD AddressLow; -} TLP_HDR_MRdWr64, *PTLP_HDR_MRdWr64; - -int pfnFT_WritePipe(PBYTE pb, DWORD cb) { - printf("writepipe: %d bytes\n", cb); - - for (int i = 0; i < cb; i++) { - printf("%d, ", (int)pb[i]); - } - - printf("\n\n"); - - return 0; -} - -BOOL DeviceFPGA_TxTlp(PBYTE pbTlp, DWORD cbTlp, BOOL fRdKeepalive, BOOL fFlush) -{ - PBYTE txbuf_pb = (PBYTE)malloc(0x1000 * 32); - DWORD txbuf_cb = 0; - - DWORD status; - PBYTE pbTx; - QWORD i; - DWORD cbTx, cbTxed = 0; - if(cbTlp & 0x3) { return FALSE; } - if(cbTlp > 4 * 4 + 128) { return FALSE; } - if(cbTlp && (txbuf_cb + (cbTlp << 1) + (fFlush ? 8 : 0) >= MAX_SIZE_TX)) { - if(!DeviceFPGA_TxTlp(NULL, 0, FALSE, TRUE)) { return FALSE; } - } - //if(ctxLC->fPrintf[LC_PRINTF_VVV]) { - // TLP_Print(ctxLC, pbTlp, cbTlp, TRUE); - //} - // prepare transmit buffer - pbTx = txbuf_pb + txbuf_cb; - cbTx = 2 * cbTlp; - for(i = 0; i < cbTlp; i += 4) { - *(PDWORD)(pbTx + (i << 1)) = *(PDWORD)(pbTlp + i); - *(PDWORD)(pbTx + ((i << 1) + 4)) = 0x77000000; // TX TLP - } - if(cbTlp) { - *(PDWORD)(pbTx + ((i << 1) - 4)) = 0x77040000; // TX TLP VALID LAST - } - if(fRdKeepalive) { - cbTx += 8; - *(PDWORD)(pbTx + (i << 1)) = 0xffeeddcc; - *(PDWORD)(pbTx + ((i << 1) + 4)) = 0x77020000; // LOOPBACK TX - } - txbuf_cb += cbTx; - // transmit - if((txbuf_cb >= MAX_SIZE_TX) || (fFlush && txbuf_cb)) { - status = pfnFT_WritePipe(txbuf_pb, txbuf_cb); - if(status == 0x20) { - //DeviceFPGA_ReInitializeFTDI(ctx); // try recovery if possible. - status = pfnFT_WritePipe(txbuf_pb, txbuf_cb); - } - txbuf_cb = 0; - //usleep(ctx->perf.DELAY_WRITE); - return (0 == status); - } - return TRUE; -} - - - -int main() -{ - DWORD tx[4] = { 0 }; - PBYTE txb = (PBYTE)tx; - PTLP_HDR_MRdWr64 hdrRd64 = (PTLP_HDR_MRdWr64)tx; - PTLP_HDR_MRdWr32 hdrRd32 = (PTLP_HDR_MRdWr32)tx; - - printf("stuff: 0x%x\n", (WORD)(0x123 >> 2)); - /* - hdrRd32->h.TypeFmt = TLP_MRd64; - hdrRd32->h.Length = (WORD)(0x123 >> 2); - */ - hdrRd32->h.TypeFmt = TLP_MRd32; - hdrRd32->h.Length = (WORD)(0x123 >> 2); - hdrRd32->RequesterID = 17; - hdrRd32->Tag = 0x80; - hdrRd32->FirstBE = 0xf; - hdrRd32->LastBE = 0xf; - - hdrRd32->Address = (DWORD)(0x6000); - //uint64_t addr = 0x100000000 + 0x6000; - //hdrRd64->AddressHigh = (DWORD)(addr >> 32); - //hdrRd64->AddressLow = (DWORD)(addr); - - //printf("sizeof 32: 0x%x\n", sizeof(TLP_HDR_MRdWr32)); - //printf("sizeof 64: 0x%x\n", sizeof(TLP_HDR_MRdWr64)); - - printf("tlp:\n"); - for (int i = 0; i < 16; i++) { - printf("%d ", (int)txb[i]); - //printf("%X ", tx[i]); - } - printf("\n"); - - for(int j = 0; j < 4; j++) { - ENDIAN_SWAP_DWORD(tx[j]); - } - - DeviceFPGA_TxTlp((PBYTE)tx, /*is32 ? 12 : 16*/ 12, FALSE, TRUE); -} diff --git a/examples/read_pcileech.rs b/examples/read_pcileech.rs deleted file mode 100644 index 4a492de..0000000 --- a/examples/read_pcileech.rs +++ /dev/null @@ -1,19 +0,0 @@ -use log::Level; - -use memflow::connector::ConnectorArgs; -use memflow_pcileech::{create_connector, PcieGen}; - -fn main() { - simple_logger::init_with_level(Level::Trace).unwrap(); - let mut conn = create_connector(&ConnectorArgs::new()).unwrap(); - conn.set_pcie_gen(PcieGen::Gen2).unwrap(); - - // TODO: put this + more in a conn print trait -> - println!( - "pcie device opened with link width {} and pcie gen {:?}", - conn.pcie_link_width(), - conn.pcie_gen() - ); - - conn.test_read().unwrap(); -} diff --git a/install.sh b/install.sh new file mode 100755 index 0000000..82c8cb8 --- /dev/null +++ b/install.sh @@ -0,0 +1,19 @@ +#!/bin/bash + +cargo build --release --all-features + +# install connector to system dir +if [ ! -z "$1" ] && [ $1 = "--system" ]; then + echo "installing connector system-wide in /usr/lib/memflow" + if [[ ! -d /usr/lib/memflow ]]; then + sudo mkdir /usr/lib/memflow + fi + sudo cp target/release/libmemflow_pcileech.so /usr/lib/memflow +fi + +# install connector in user dir +echo "installing connector for user in ~/.local/lib/memflow" +if [[ ! -d ~/.local/lib/memflow ]]; then + mkdir -p ~/.local/lib/memflow +fi +cp target/release/libmemflow_pcileech.so ~/.local/lib/memflow diff --git a/leechcore-sys/Cargo.toml b/leechcore-sys/Cargo.toml new file mode 100644 index 0000000..a86cc0c --- /dev/null +++ b/leechcore-sys/Cargo.toml @@ -0,0 +1,14 @@ +[package] +name = "leechcore-sys" +version = "0.1.0" +authors = ["ko1N "] +edition = "2018" +readme = "../README.md" +license-file = "../LICENSE" + +links = "leechcore" + +[build-dependencies] +cc = "1.0.62" +bindgen = "0.55" +pkg-config = "0.3" diff --git a/leechcore-sys/build.rs b/leechcore-sys/build.rs new file mode 100644 index 0000000..ebaa9a1 --- /dev/null +++ b/leechcore-sys/build.rs @@ -0,0 +1,82 @@ +extern crate bindgen; +extern crate cc; +extern crate pkg_config; + +use std::env; +use std::path::PathBuf; +use std::process::Command; + +#[cfg(target_os = "windows")] +fn os_define() -> &'static str { + "_WIN32" +} + +#[cfg(target_os = "linux")] +fn os_define() -> &'static str { + "LINUX" +} + +fn main() -> () { + //let target = env::var("TARGET").unwrap(); + let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap()); + + let objs = vec![ + "oscompatibility.c", + "leechcore.c", + "util.c", + "memmap.c", + "device_file.c", + "device_fpga.c", + "device_pmem.c", + "device_tmd.c", + "device_usb3380.c", + "leechrpcclient.c", + ]; + + pkg_config::probe_library("libusb-1.0") + .unwrap_or_else(|err| panic!("Failed to find libusb-1.0 via pkg-config: {:?}", err)); + + // TODO: windows + // TODO: pkg_config ? + let libusb_flags = Command::new("pkg-config") + .args(&["libusb-1.0", "--libs", "--cflags"]) + .output() + .unwrap_or_else(|err| panic!("Failed to find libusb-1.0 via pkg-config: {:?}", err)); + + let mut cfg = cc::Build::new(); + cfg.cpp(false) + .files( + objs.iter() + .map(|o| "src/leechcore/leechcore/".to_string() + o) + .collect::>(), + ) + .flag(&format!("-D{}", os_define())) + .flag("-fPIC") + .flag("-fvisibility=hidden") + .flag("-pthread") + .flag("-g") + .flag("-ldl"); + + for flag in String::from_utf8_lossy(&libusb_flags.stdout) + .trim() + .split(" ") + { + cfg.flag(flag); + } + + cfg.compile("libleechcore.a"); + + // generate bindings + let bindings = bindgen::builder() + .clang_arg(format!("-D{}", os_define())) + .header("./src/leechcore/leechcore/leechcore.h") + .generate() + .unwrap_or_else(|err| panic!("Failed to generate bindings: {:?}", err)); + + let bindings_path = out_dir.join("leechcore.rs"); + bindings + .write_to_file(&bindings_path) + .unwrap_or_else(|_| panic!("Failed to write {}", bindings_path.display())); + + println!("cargo:rustc-link-lib=static=leechcore"); +} diff --git a/leechcore-sys/src/leechcore b/leechcore-sys/src/leechcore new file mode 160000 index 0000000..9a744a3 --- /dev/null +++ b/leechcore-sys/src/leechcore @@ -0,0 +1 @@ +Subproject commit 9a744a313a023bde5b8e710597f3690a27561906 diff --git a/leechcore-sys/src/lib.rs b/leechcore-sys/src/lib.rs new file mode 100644 index 0000000..780a4ea --- /dev/null +++ b/leechcore-sys/src/lib.rs @@ -0,0 +1,8 @@ +#![allow(non_snake_case)] +#![allow(non_camel_case_types)] +#![allow(non_upper_case_globals)] +#![allow(clippy::useless_transmute)] +#![allow(clippy::cognitive_complexity)] +#![allow(clippy::missing_safety_doc)] + +include!(concat!(env!("OUT_DIR"), "/leechcore.rs")); diff --git a/memflow-pcileech/Cargo.toml b/memflow-pcileech/Cargo.toml new file mode 100644 index 0000000..0b960ee --- /dev/null +++ b/memflow-pcileech/Cargo.toml @@ -0,0 +1,40 @@ +[package] +name = "memflow-pcileech" +version = "0.1.0" +authors = ["ko1N "] +edition = "2018" +description = "qemu procfs connector for leechcore/pcileech" +documentation = "https://docs.rs/memflow-pcileech" +readme = "../README.md" +homepage = "https://memflow.github.io" +repository = "https://github.com/memflow/memflow-pcileech" +license-file = "../LICENSE" +keywords = [ "memflow", "introspection", "memory" ] +categories = [ "api-bindings", "memory-management", "os" ] + +[lib] +crate-type = ["lib", "cdylib"] + +[dependencies] +memflow = { version = "0.1", features = ["inventory"] } +memflow-derive = { version = "0.1" } +log = { version = "0.4", default-features = false } +leechcore-sys = { path = "../leechcore-sys" } + +# test +libc = "0.2" + +[dev-dependencies] +clap = "2.33" +simple_logger = "1.0" + +[profile.release] +lto = true + +[features] +default = [] +inventory = [] + +[[example]] +name = "read_phys" +path = "examples/read_phys.rs" diff --git a/memflow-pcileech/examples/read_phys.rs b/memflow-pcileech/examples/read_phys.rs new file mode 100644 index 0000000..fcecfba --- /dev/null +++ b/memflow-pcileech/examples/read_phys.rs @@ -0,0 +1,48 @@ +use std::time::Instant; + +use log::{info, Level}; + +use memflow::*; + +fn main() { + simple_logger::init_with_level(Level::Debug).unwrap(); + + // TODO: parse command-line args + /* + let mut conn = match memflow_pcileech::create_connector( + &ConnectorArgs::parse("name=win10,type=kvm").unwrap(), + ) { + Ok(br) => br, + Err(e) => { + info!("couldn't open memory read context: {:?}", e); + return; + } + }; + */ + let mut conn = memflow_pcileech::PciLeech::new("FPGA").unwrap(); + info!("conn: {:?}", conn); + + let mut mem = vec![0; 8]; + conn.phys_read_raw_into(Address::from(0x1000).into(), &mut mem) + .unwrap(); + info!("Received memory: {:?}", mem); + + /* + let start = Instant::now(); + let mut counter = 0; + loop { + let mut buf = vec![0; 0x1000]; + conn.phys_read_raw_into(Address::from(0x1000).into(), &mut buf) + .unwrap(); + + counter += 1; + if (counter % 10000) == 0 { + let elapsed = start.elapsed().as_millis() as f64; + if elapsed > 0.0 { + info!("{} reads/sec", (f64::from(counter)) / elapsed * 1000.0); + info!("{} ms/read", elapsed / (f64::from(counter))); + } + } + } + */ +} diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs new file mode 100644 index 0000000..3892c26 --- /dev/null +++ b/memflow-pcileech/src/lib.rs @@ -0,0 +1,170 @@ +// https://github.com/ufrisk/pcileech/blob/master/pcileech/device.c + +use std::ffi::CString; +use std::os::raw::c_char; + +use libc::malloc; +use log::{error, info, warn}; + +use memflow::*; +use memflow_derive::connector; + +use leechcore_sys::*; + +fn build_lc_config(device: &str) -> LC_CONFIG { + let cdevice = unsafe { &*(device.as_bytes() as *const [u8] as *const [i8]) }; + let mut adevice: [c_char; 260] = [0; 260]; + // adevice.clone_from_slice(unsafe { &*(cdevice.as_bytes_with_nul() as *const [u8] as *const [i8]) }); + adevice[..device.len().min(260)].copy_from_slice(&cdevice[..device.len().min(260)]); + + let cfg = LC_CONFIG { + dwVersion: LC_CONFIG_VERSION, + dwPrintfVerbosity: LC_CONFIG_PRINTF_ENABLED | LC_CONFIG_PRINTF_V | LC_CONFIG_PRINTF_VV, + szDevice: adevice, + szRemote: [0; 260], + pfn_printf_opt: None, // TODO: custom info() wrapper + paMax: 0, + fVolatile: 0, + fWritable: 0, + fRemote: 0, + fRemoteDisableCompress: 0, + szDeviceName: [0; 260], + }; + + // TODO: copy device + remote + + cfg +} + +#[derive(Debug)] +pub struct PciLeech { + handle: HANDLE, +} + +// TODO: +unsafe impl Send for PciLeech {} + +// TODO: implement me +impl Clone for PciLeech { + fn clone(&self) -> Self { + panic!("unable to clone pcileech connector"); + } +} + +// TODO: proper drop + free impl -> LcMemFree(pLcErrorInfo); +impl PciLeech { + pub fn new(device: &str) -> Result { + // open device + let mut conf = build_lc_config(device); + let err = std::ptr::null_mut::(); + let handle = unsafe { LcCreateEx(&mut conf, err) }; + if handle.is_null() { + // TODO: handle version error + // TODO: handle special case of fUserInputRequest + error!("leechcore error: {:?}", err); + return Err(Error::Connector("unable to create leechcore context")); + } + + Ok(Self { handle }) + } +} + +impl PhysicalMemory for PciLeech { + fn phys_read_raw_list(&mut self, data: &mut [PhysicalReadData]) -> Result<()> { + // TODO: everything apart from 0x1000 byte buffers crashes... + for read in data.iter_mut() { + // TODO: ensure reading just 1 page... + // TODO: handle page boundaries + if read.1.len() < 0x1000 { + let mut page = [0u8; 0x1000]; + let aligned = read.0.address().as_page_aligned(0x1000); + unsafe { + LcRead( + self.handle, + aligned.as_u64(), + page.len() as u32, + page.as_mut_ptr(), + ) + }; + let offs = (read.0.as_u64() - aligned.as_u64()) as usize; + read.1.copy_from_slice(&page[offs..offs + read.1.len()]); + } else { + // TODO: handle multiple pages at once + // TODO: handle page alignment + unsafe { + LcRead( + self.handle, + read.0.as_u64(), + read.1.len() as u32, + read.1.as_mut_ptr(), + ) + }; + } + } + Ok(()) + } + + fn phys_write_raw_list(&mut self, data: &[PhysicalWriteData]) -> Result<()> { + // TODO: everything apart from 0x1000 byte buffers crashes... + unsafe { + for write in data.iter() { + LcWrite( + self.handle, + write.0.as_u64(), + write.1.len() as u32, + write.1.as_ptr() as *mut u8, + ); + + /* + // TODO: ensure reading just 1 page... + // TODO: handle page boundaries + if write.1.len() < 0x1000 { + let mut page = [0u8; 0x1000]; + let aligned = write.0.address().as_page_aligned(0x1000); + unsafe { + LcRead( + self.handle, + aligned.as_u64(), + page.len() as u32, + page.as_mut_ptr(), + ) + }; + let offs = (read.0.as_u64() - aligned.as_u64()) as usize; + read.1.copy_from_slice( + &page[offs..offs+read.1.len()], + ); + } else { + // TODO: handle multiple pages at once + // TODO: handle page alignment + unsafe { + LcRead( + self.handle, + read.0.as_u64(), + read.1.len() as u32, + read.1.as_mut_ptr(), + ) + }; + } + */ + } + } + Ok(()) + } + + fn metadata(&self) -> PhysicalMemoryMetadata { + PhysicalMemoryMetadata { + size: size::gb(16), // TODO: + readonly: false, + } + } +} + +/// Creates a new PciLeech Connector instance. +#[connector(name = "pcileech")] +pub fn create_connector(args: &ConnectorArgs) -> Result { + let device = args + .get("device") + .or_else(|| args.get_default()) + .ok_or(Error::Connector("argument 'device' missing"))?; + PciLeech::new(device) +} diff --git a/src/fpga.rs b/src/fpga.rs deleted file mode 100644 index 08c4153..0000000 --- a/src/fpga.rs +++ /dev/null @@ -1,800 +0,0 @@ -// TODO: unpub? -pub mod tlps; -use tlps::*; - -use crate::ft60x::*; - -use core::mem::MaybeUninit; -use core::time::Duration; - -use log::{info, trace, warn}; - -use memflow::{ - error::{Error, Result}, - size, -}; - -use c2rust_bitfields::*; -use dataview::Pod; -use pretty_hex::*; - -pub const FPGA_CONFIG_CORE: u16 = 0x0003; -pub const FPGA_CONFIG_PCIE: u16 = 0x0001; -pub const FPGA_CONFIG_SPACE_READONLY: u16 = 0x0000; -pub const FPGA_CONFIG_SPACE_READWRITE: u16 = 0x8000; - -// TODO: remove unused -#[allow(unused)] -pub struct PhyConfig { - magic: u8, // 8 bit - tp_cfg: u8, // 4 bit - tp: u8, // 4 bit - pub wr: PhyConfigWr, // 16 bits - pub rd: PhyConfigRd, // 32 bits -} - -#[repr(C, align(1))] -#[derive(BitfieldStruct, Pod)] -pub struct PhyConfigWr { - #[bitfield(name = "pl_directed_link_auton", ty = "libc::uint8_t", bits = "0..=0")] - #[bitfield(name = "pl_directed_link_change", ty = "libc::uint8_t", bits = "1..=2")] - #[bitfield(name = "pl_directed_link_speed", ty = "libc::uint8_t", bits = "3..=3")] - #[bitfield(name = "pl_directed_link_width", ty = "libc::uint8_t", bits = "4..=5")] - #[bitfield(name = "pl_upstream_prefer_deemph", ty = "libc::uint8_t", bits = "6..=6")] - #[bitfield(name = "pl_transmit_hot_rst", ty = "libc::uint8_t", bits = "7..=7")] - #[bitfield(name = "pl_downstream_deemph_source", ty = "libc::uint8_t", bits = "8..=8")] - buffer: [u8; 2], -} -const _: [(); core::mem::size_of::()] = [(); 2]; - -#[repr(C, align(1))] -#[derive(BitfieldStruct, Pod)] -pub struct PhyConfigRd { - #[bitfield(name = "pl_ltssm_state", ty = "libc::uint8_t", bits = "0..=5")] - #[bitfield(name = "pl_rx_pm_state", ty = "libc::uint8_t", bits = "6..=7")] - #[bitfield(name = "pl_tx_pm_state", ty = "libc::uint8_t", bits = "8..=10")] - #[bitfield(name = "pl_initial_link_width", ty = "libc::uint8_t", bits = "11..=13")] - #[bitfield(name = "pl_lane_reversal_mode", ty = "libc::uint8_t", bits = "14..=15")] - #[bitfield(name = "pl_sel_lnk_width", ty = "libc::uint8_t", bits = "16..=17")] - #[bitfield(name = "pl_phy_lnk_up", ty = "libc::uint8_t", bits = "18..=18")] - #[bitfield(name = "pl_link_gen2_cap", ty = "libc::uint8_t", bits = "19..=19")] - #[bitfield(name = "pl_link_partner_gen2_supported", ty = "libc::uint8_t", bits = "20..=20")] - #[bitfield(name = "pl_link_upcfg_cap", ty = "libc::uint8_t", bits = "21..=21")] - #[bitfield(name = "pl_sel_lnk_rate", ty = "libc::uint8_t", bits = "22..=22")] - #[bitfield(name = "pl_directed_change_done", ty = "libc::uint8_t", bits = "23..=23")] - #[bitfield(name = "pl_received_hot_rst", ty = "libc::uint8_t", bits = "24..=24")] - buffer: [u8; 4], -} -const _: [(); core::mem::size_of::()] = [(); 4]; - -pub struct Device { - ft60: FT60x, -} - -impl Device { - pub fn new() -> Result { - let mut ft60 = FT60x::new()?; - ft60.abort_pipe(0x02)?; - ft60.abort_pipe(0x82)?; - - ft60.set_suspend_timeout(Duration::new(0, 0))?; - - // check chip configuration - let mut conf = ft60.config()?; - info!( - "ft60x config: fifo_mode={} channel_config={} optional_feature={}", - conf.fifo_mode, conf.channel_config, conf.optional_feature_support - ); - - if conf.fifo_mode != FifoMode::Mode245 as i8 - || conf.channel_config != ChannelConfig::Config1 as i8 - || conf.optional_feature_support != OptionalFeatureSupport::DisableAll as i16 - { - warn!("bad ft60x config, reconfiguring chip"); - - conf.fifo_mode = FifoMode::Mode245 as i8; - conf.channel_config = ChannelConfig::Config1 as i8; - conf.optional_feature_support = OptionalFeatureSupport::DisableAll as i16; - - ft60.set_config(&conf)?; - } else { - info!("ft60x config is valid"); - } - - Ok(Self { ft60 }) - } - - /// Restarts the PCIE device - fn reset_core(&mut self) -> Result<()> { - let reset_code: [u8; 2] = [0x00, 0x80]; - self.write_config_ex_raw( - 0x0002, - reset_code, - reset_code, - FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READWRITE, - )?; - std::thread::sleep(Duration::from_millis(1000)); - self.ft60 = FT60x::new()?; - Ok(()) - } - - /// Clears the pipe before starting any new read attempts - pub fn clear_pipe(&mut self) -> Result<()> { - let dummy = [ - // dword->qword resynch v4.5+ - 0x66, 0x66, 0x55, 0x55, 0x66, 0x66, 0x55, 0x55, 0x66, 0x66, 0x55, 0x55, 0x66, 0x66, - 0x55, 0x55, // cmd msg: FPGA bitstream version (major.minor) v4 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x13, 0x77, - // cmd msg: FPGA bitstream version (major) v3 - 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x77, - ]; - - //self.reset_core()?; - - self.ft60.write_pipe(&dummy)?; - - let mut buf = vec![0u8; size::mb(1)]; - if self.ft60.read_pipe(&mut buf[..0x1000])? >= 0x1000 { - if self.ft60.read_pipe(&mut buf)? == buf.len() { - self.reset_core()?; - } - } - - Ok(()) - } - - pub fn read_version(&mut self) -> Result<(u8, u8)> { - let version_major = - self.read_config::(0x0008, FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY)?; - info!("version_major = {}", version_major); - - let version_minor = - self.read_config::(0x0009, FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY)?; - info!("version_minor={}", version_minor); - - Ok((version_major, version_minor)) - } - - pub fn read_devid(&mut self) -> Result<(u8, u16)> { - let fpga_id = - self.read_config::(0x000a, FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY)?; - info!("fpga_id={}", fpga_id); - - let mut device_id = self - .read_config::(0x0008, FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READONLY) - .unwrap_or_default(); - if device_id == 0 { - info!("pci device_id is unset. checking pcie magic."); - - let magic_pcie = self - .read_config::(0x0000, FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READWRITE) - .unwrap_or_default(); - info!("magic_pcie={:?}", magic_pcie); - - if magic_pcie == 0x6745 { - warn!("failed to get device_id. trying to recover via hot reset"); - self.hot_reset().ok(); - device_id = self - .read_config::(0x0008, FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READONLY) - .unwrap_or_default(); - } - } - let device_id_le = device_id.to_be(); - info!("device_id={:?}", device_id_le); - - // swap device_id bytes only on LE systems - Ok((fpga_id, device_id_le)) - } - - pub fn write_inactivity_timer(&mut self) -> Result<()> { - let inactivity_timer = 0x000186a0u32; // set inactivity timer to 1ms (0x0186a0 * 100MHz) [only later activated on UDP bitstreams] - self.write_config( - 0x0008, - inactivity_timer, - FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READWRITE, - ) - } - - pub fn hot_reset(&mut self) -> Result<()> { - warn!("hot resetting the fpga"); - - let mut wr = self.get_phy_wr()?; - wr.set_pl_transmit_hot_rst(1); - self.set_phy_wr(&wr)?; - - std::thread::sleep(Duration::from_millis(250)); // TODO: poll pl_ltssm_state + timeout with failure - - wr.set_pl_transmit_hot_rst(0); - self.set_phy_wr(&wr)?; - Ok(()) - } - - pub fn get_phy(&mut self) -> Result<(PhyConfigWr, PhyConfigRd)> { - Ok((self.get_phy_wr()?, self.get_phy_rd()?)) - } - - pub fn get_phy_wr(&mut self) -> Result { - let wr_raw = - self.read_config::(0x0016, FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READWRITE)?; - Ok(PhyConfigWr { buffer: u16::to_le_bytes(wr_raw) }) - } - - pub fn set_phy_wr(&mut self, wr: &PhyConfigWr) -> Result<()> { - self.write_config(0x0016, u16::from_le_bytes(wr.buffer), FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READWRITE) - } - - pub fn get_phy_rd(&mut self) -> Result { - let rd_raw = - self.read_config::(0x000a, FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READONLY)?; - Ok(PhyConfigRd { buffer: u32::to_le_bytes(rd_raw) }) - } - - /// Prints out all internal registers of the FPGA to `info!()` - /// In detail this will request the core/pcie readonly and read/write registers - /// and print them out via `info!()`. This is usually useful when debugging any - /// issues with the hardware. - pub fn print_registers(&mut self) -> Result<()> { - info!( - "core read-only registers: {:?}", - self.get_register(FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY)? - .hex_dump() - ); - info!( - "core read-write registers: {:?}", - self.get_register(FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READWRITE)? - .hex_dump() - ); - info!( - "pcie read-only registers: {:?}", - self.get_register(FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READONLY)? - .hex_dump() - ); - info!( - "core read-write registers: {:?}", - self.get_register(FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READWRITE)? - .hex_dump() - ); - Ok(()) - } - - fn get_register(&mut self, flags: u16) -> Result> { - let size = self.read_config::(0x0004, flags)?; - info!( - "reading fpga device config register {:x} with a length of {:x} bytes.", - flags, size - ); - let mut buf = vec![0u8; size as usize]; - self.read_config_into_raw(0x0000, &mut buf[..], flags)?; - Ok(buf) - } - - // TODO: implement more config dump options - fn get_pcie_drp(&mut self) { - let read_enable = [0x10, 0x00, 0x10, 0x00, 0x80, 0x02, 0x23, 0x77]; - let read_address = [0x00, 0x00, 0xff, 0xff, 0x80, 0x1c, 0x23, 0x77]; - let result_meta = [0x00, 0x00, 0x00, 0x00, 0x80, 0x1c, 0x13, 0x77]; - let result_data = [0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x13, 0x77]; - - // create read request - for addr in (0..0x100).step_by(32) { - for dw in (0..32).step_by(2) {} - } - - // interpret result - } - - // TODO: send_tlp_ ... - /*pub fn send_tlp32(&mut self, tlp: u32, keep_alive: bool, flush: bool) -> Result<()> { - self.send_tlp_raw(tlp.as_bytes(), keep_alive, flush) - } - - pub fn send_tlp64(&mut self, tlp: u64, keep_alive: bool, flush: bool) -> Result<()> { - self.send_tlp_raw(tlp.as_bytes(), keep_alive, flush) - }*/ - - // TODO: this is duplicated code (see config_parse_response) - // https://github.com/ufrisk/LeechCore/blob/master/leechcore/device_fpga.c#L1603 - pub fn recv_tlps_64(&mut self, bytes: u32 /* maybe u16? */) -> Result<()> { - let mut respbuf = vec![0u8; 0x4000]; // TEST - self.ft60.read_pipe(&mut respbuf)?; - - //let tlps = [0u8; 16+512]; // TLP_RX_MAX_SIZE - //let tlp_num = 0; - let mut tlps = Vec::new(); - - let view = respbuf.as_data_view(); - let mut skip = 0; - for i in (0..respbuf.len()).step_by(32) { - if i + skip >= respbuf.len() { - break; - } - - while view.copy::(i + skip) == 0x55556666 { - trace!("ftdi workaround detected, skipping 4 bytes"); - skip += 4; - if i + skip + 32 > respbuf.len() { - return Err(Error::Connector("out of range config read")); - } - } - - let mut status = view.copy::(i + skip); - if status & 0xf0000000 != 0xe0000000 { - trace!("invalid status reply, skipping"); - continue; - } - - //trace!("parsing tlp data buffer"); - let mut tlp_offs = 0; - for _ in 0..7 { - if (status & 0x03) == 0 { - // println!("pcie tlp received :)"); - tlps.push(view.copy::(i + skip + 4 + tlp_offs)); - // if(tlps.len() >= TLP_RX_MAX_SIZE / sizeof(DWORD)) { return; } - } - if (status & 0x07) == 4 { - //println!("pcie tlp LAST received :)"); - // TODO: dispatch tlp buffer - if tlps.len() >= 3 { - println!("received {} tlps", tlps.len() << 2); - // TODO: transmute tlps buffer to tlp header - - } else { - println!("received {} tlps - ERROR, Bad PCIe TLP received", tlps.len() << 2); - } - tlps.clear(); - } - tlp_offs += 4; - status >>= 4; - } - } - - Ok(()) - } - - fn read_mem_build_request(bytes: &[u8], keep_alive: bool) -> Result> { - // convert slice into [u32] slice which is 4 times smaller - let dwords = - unsafe { std::slice::from_raw_parts(bytes.as_ptr() as *const u32, bytes.len() / 4) }; - - // tlp buffer constraints - if (bytes.len() & 0x3) != 0 || bytes.len() > 4 * 4 + 128 { - return Err(Error::Connector("tlp buffer is too large")); - } - /* - if(cbTlp && (txbuf_cb + (cbTlp << 1) + (fFlush ? 8 : 0) >= MAX_SIZE_TX)) { - if(!DeviceFPGA_TxTlp(NULL, 0, FALSE, TRUE)) { return FALSE; } - } - */ - - // TLP_Print - - // create transmit buffer - let mut buf = Vec::new(); - for tlp in dwords.iter() { - buf.push(tlp.to_be()); - buf.push(0x77000000); // TX TLP - } - - // TODO: remove this pop in the algorithm - if !bytes.is_empty() { - buf.pop(); - buf.push(0x77040000); // TX TLP VALID LAST - } - - if keep_alive { - buf.push(0xffeeddcc); - buf.push(0x77020000); - } - - // currently we just flush out every tlp transmission immediately - // and not buffer them internally. - let byte_buf = buf - .iter() - .map(|&t| u32::to_le_bytes(t)) - .collect::>() - .concat(); - - Ok(byte_buf.to_vec()) - } - - pub fn read_mem_into_raw(&mut self, addr: u64, size: u64, device_id: u16) -> Result<()> { - - // TODO: safety checks - // TODO: split by page and page align - - let tlp = if addr < size::gb(4) as u64 { - TlpReadWrite32::new_read(addr as u32, size as u16, 0x0, device_id).as_bytes().to_vec() - } else { - TlpReadWrite64::new_read(addr, size as u16, 0x0, device_id).as_bytes().to_vec() - }; - let req = Self::read_mem_build_request(tlp.as_slice(), false)?; - - self.ft60.write_pipe(&req)?; - - std::thread::sleep(std::time::Duration::from_millis(500)); - - self.recv_tlps_64(0x1000)?; - - /* - let mut readbuf = [0u8; size::kb(128)]; - let bytes = self.ft60.read_pipe(&mut readbuf)?; - - Self::read_config_parse_response(addr, &readbuf[..bytes], buf, flags) - */ - - Ok(()) - } - - #[allow(clippy::uninit_assumed_init)] - fn read_config(&mut self, addr: u16, flags: u16) -> Result { - let mut obj: T = unsafe { MaybeUninit::uninit().assume_init() }; - self.read_config_into_raw(addr, obj.as_bytes_mut(), flags)?; - Ok(obj) - } - - fn read_config_build_request(addr: u16, bytes: u16, flags: u16) -> Vec { - let mut res = Vec::new(); - for a in (addr..addr + bytes).step_by(2) { - let mut req = [0u8; 8]; - req[4] = ((a | (flags & 0x8000)) >> 8) as u8; - req[5] = (a & 0xff) as u8; - req[6] = (0x10 | (flags & 0x03)) as u8; - req[7] = 0x77; - res.extend_from_slice(&req); - } - res - } - - fn read_config_parse_response( - addr: u16, - respbuf: &[u8], - outbuf: &mut [u8], - flags: u16, - ) -> Result<()> { - let view = respbuf.as_data_view(); - let mut skip = 0; - for i in (0..respbuf.len()).step_by(32) { - if i + skip >= respbuf.len() { - break; - } - - while view.copy::(i + skip) == 0x55556666 { - //trace!("ftdi workaround detected, skipping 4 bytes"); - skip += 4; - if i + skip + 32 > respbuf.len() { - return Err(Error::Connector("out of range config read")); - } - } - - let mut status = view.copy::(i + skip); - if status & 0xf0000000 != 0xe0000000 { - trace!("invalid status reply, skipping"); - } - - trace!("parsing data buffer"); - for j in 0..7 { - let status_flag = (status & 0x0f) == (flags & 0x03) as u32; - status >>= 4; // move to next status - if !status_flag { - //trace!("status source flag does not match source"); - continue; - } - - let data = view.copy::(i + skip + 4 + j * 4); - let mut a = (data as u16).to_be(); // only enforce a byteswap if we are on le - a -= (flags & 0x8000) + addr; - if a >= outbuf.len() as u16 { - trace!("address data out of range, skipping"); - continue; - } - - if a == outbuf.len() as u16 - 1 { - outbuf[a as usize] = ((data >> 16) & 0xff) as u8; - } else { - let b = (((data >> 16) & 0xffff) as u16).to_le_bytes(); - outbuf[a as usize] = b[0]; - outbuf[a as usize + 1] = b[1]; - } - } - } - Ok(()) - } - - fn read_config_into_raw(&mut self, addr: u16, buf: &mut [u8], flags: u16) -> Result<()> { - if buf.is_empty() || buf.len() > size::kb(4) || addr > size::kb(4) as u16 { - return Err(Error::Connector("invalid config address requested")); - } - - let req = Self::read_config_build_request(addr, buf.len() as u16, flags); - - self.ft60.write_pipe(&req)?; - - let mut readbuf = [0u8; size::kb(128)]; - let bytes = self.ft60.read_pipe(&mut readbuf)?; - - Self::read_config_parse_response(addr, &readbuf[..bytes], buf, flags) - } - - fn write_config(&mut self, addr: u16, obj: T, flags: u16) -> Result<()> { - self.write_config_raw(addr, obj.as_bytes(), flags) - } - - fn write_config_build_request(addr: u16, buf: &[u8], flags: u16) -> Result> { - if buf.is_empty() || buf.len() > 0x200 || addr > size::kb(4) as u16 { - return Err(Error::Connector("invalid config address to write")); - } - - let mut outbuf = [0u8; 0x800]; - let mut ptr = 0; - for i in (0..buf.len()).step_by(2) { - let a = (addr + i as u16) | (flags & 0x8000); - outbuf[ptr] = buf[i as usize]; // byte_value_addr - outbuf[ptr + 1] = if buf.len() == i + 1 { - 0 - } else { - buf[i as usize + 1] - }; // byte_value_addr + 1 - outbuf[ptr + 2] = 0xFF; // byte_mask_addr - outbuf[ptr + 3] = if buf.len() == i + 1 { 0 } else { 0xFF }; // byte_mask_addr + 1 - outbuf[ptr + 4] = (a >> 8) as u8; // addr_high = bit[6:0], write_regbank = bit[7] - outbuf[ptr + 5] = (a & 0xFF) as u8; // addr_low - outbuf[ptr + 6] = (0x20 | (flags & 0x03)) as u8; // target = bit[0:1], read = bit[4], write = bit[5] - outbuf[ptr + 7] = 0x77; // MAGIC 0x77 - ptr += 8; - } - - Ok(outbuf[..ptr].to_vec()) - } - - fn write_config_raw(&mut self, addr: u16, buf: &[u8], flags: u16) -> Result<()> { - let outbuf = Self::write_config_build_request(addr, buf, flags)?; - self.ft60.write_pipe(&outbuf) - } - - fn write_config_ex_build_request( - addr: u16, - buf: [u8; 2], - mask: [u8; 2], - flags: u16, - ) -> Result<[u8; 8]> { - let a = (addr as u16) | (flags & 0x8000); - Ok([ - buf[0], - buf[1], - mask[0], - mask[1], - (a >> 8) as u8, // addr_high - (a & 0xFF) as u8, // addr_low - (0x20 | (flags & 0x03)) as u8, // target = bit[0:1], read = bit[4], write = bit[5] - 0x77, // MAGIC 0x77 - ]) - } - - fn write_config_ex_raw( - &mut self, - addr: u16, - buf: [u8; 2], - mask: [u8; 2], - flags: u16, - ) -> Result<()> { - let outbuf = Self::write_config_ex_build_request(addr, buf, mask, flags)?; - self.ft60.write_pipe(&outbuf) - } -} - -#[cfg(test)] -mod tests { - use super::*; - use core::mem::size_of; - - #[test] - fn test_struct_sizes() { - assert_eq!(size_of::(), 2); - assert_eq!(size_of::(), 4); - } - - #[test] - fn test_config_read_build_request() { - assert_eq!( - Device::read_config_build_request( - 0x0008, - 1, - FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY - ), - [0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0x13, 0x77] - ); - assert_eq!( - Device::read_config_build_request( - 0x0009, - 1, - FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY - ), - [0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x13, 0x77] - ); - - assert_eq!( - Device::read_config_build_request( - 0x0008, - 2, - FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READONLY - ), - [0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0x11, 0x77] - ); - assert_eq!( - Device::read_config_build_request( - 0x0000, - 2, - FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READWRITE - ), - [0x0, 0x0, 0x0, 0x0, 0x80, 0x0, 0x11, 0x77] - ); - - assert_eq!( - Device::read_config_build_request( - 0x0016, - 2, - FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READWRITE - ), - [0x0, 0x0, 0x0, 0x0, 0x80, 0x16, 0x11, 0x77] - ); - assert_eq!( - Device::read_config_build_request( - 0x000a, - 4, - FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READONLY - ), - [0x0, 0x0, 0x0, 0x0, 0x0, 0xA, 0x11, 0x77, 0x0, 0x0, 0x0, 0x0, 0x0, 0xC, 0x11, 0x77] - ); - } - - #[test] - fn test_config_parse_version_major() { - let mut version_major = 0u8; - Device::read_config_parse_response( - 0x0008, - &[ - 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, - 85, 85, 243, 255, 255, 239, 0, 8, 4, 2, 255, 255, 255, 255, 255, 255, 255, 255, - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, - ], - version_major.as_bytes_mut(), - FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY, - ) - .unwrap(); - assert_eq!(version_major, 4); - } - - #[test] - fn test_config_parse_version_minor() { - let mut version_minor = 0u8; - Device::read_config_parse_response( - 0x0009, - &[ - 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, - 85, 85, 243, 255, 255, 239, 0, 9, 2, 1, 255, 255, 255, 255, 255, 255, 255, 255, - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, - ], - version_minor.as_bytes_mut(), - FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY, - ) - .unwrap(); - assert_eq!(version_minor, 2); - } - - #[test] - fn test_config_parse_fpga_id() { - let mut fpga_id = 0u8; - Device::read_config_parse_response( - 0x000a, - &[ - 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, - 85, 85, 243, 255, 255, 239, 0, 10, 1, 0, 255, 255, 255, 255, 255, 255, 255, 255, - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, - ], - fpga_id.as_bytes_mut(), - FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY, - ) - .unwrap(); - assert_eq!(fpga_id, 1); - } - - #[test] - fn test_config_parse_device_id() { - let mut fpga_id = 0u8; - Device::read_config_parse_response( - 0x000a, - &[ - 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, - 85, 85, 243, 255, 255, 239, 0, 10, 1, 0, 255, 255, 255, 255, 255, 255, 255, 255, - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, - ], - fpga_id.as_bytes_mut(), - FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READONLY, - ) - .unwrap(); - assert_eq!(fpga_id, 1); - } - - #[test] - fn test_config_parse_phy_wr() { - let mut wr = 0u16; - Device::read_config_parse_response( - 0x0016, - &[ - 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, - 85, 85, 241, 255, 255, 239, 128, 22, 72, 0, 255, 255, 255, 255, 255, 255, 255, 255, - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, - ], - wr.as_bytes_mut(), - FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READWRITE, - ) - .unwrap(); - assert_eq!(wr, 0x48); - } - - #[test] - fn test_config_parse_phy_rd() { - let mut rd = 0u32; - Device::read_config_parse_response( - 0x000a, - &[ - 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, 85, 85, 102, 102, - 85, 85, 17, 255, 255, 239, 0, 10, 25, 8, 0, 12, 28, 0, 255, 255, 255, 255, 255, - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, - ], - rd.as_bytes_mut(), - FPGA_CONFIG_PCIE | FPGA_CONFIG_SPACE_READONLY, - ) - .unwrap(); - assert_eq!(rd, 0x1C0819); - } - - #[test] - fn write_config_inactivity_timer() { - let inactivity_timer = 0x000186a0u32; // set inactivity timer to 1ms (0x0186a0 * 100MHz) [only later activated on UDP bitstreams] - let outbuf = Device::write_config_build_request( - 0x0008, - inactivity_timer.as_bytes(), - FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READWRITE, - ) - .unwrap(); - assert_eq!( - outbuf, - [160, 134, 255, 255, 128, 8, 35, 119, 1, 0, 255, 255, 128, 10, 35, 119] - ); - } - - #[test] - fn write_config_core_reset() { - let code: [u8; 2] = [0x00, 0x80]; - let outbuf = Device::write_config_ex_build_request( - 0x0002, - code, - code, - FPGA_CONFIG_CORE | FPGA_CONFIG_SPACE_READWRITE, - ) - .unwrap(); - assert_eq!(outbuf, [0, 128, 0, 128, 128, 2, 35, 119,]); - } - - #[test] - fn test_read_mem32() { - let tlp = TlpReadWrite32::new_read(0x6000, 0x123, 0x80, 17); - assert_eq!( - Device::read_mem_build_request(&tlp.as_bytes(), false).unwrap(), - [0, 0, 0, 72, 0, 0, 0, 119, 0, 17, 128, 255, 0, 0, 0, 119, 0, 0, 96, 0, 0, 0, 4, 119] - ); - } - - #[test] - fn test_read_mem64() { - let tlp = TlpReadWrite64::new_read(size::gb(4) as u64 + 0x6000, 0x123, 0x80, 17); - assert_eq!( - Device::read_mem_build_request(&tlp.as_bytes(), false).unwrap(), - [ - 32, 0, 0, 72, 0, 0, 0, 119, 0, 17, 128, 255, 0, 0, 0, 119, 0, 0, 0, 1, 0, 0, 0, - 119, 0, 0, 96, 0, 0, 0, 4, 119 - ] - ); - } -} diff --git a/src/fpga/tlps.rs b/src/fpga/tlps.rs deleted file mode 100644 index e337650..0000000 --- a/src/fpga/tlps.rs +++ /dev/null @@ -1,181 +0,0 @@ -use c2rust_bitfields::*; -use dataview::{DataView, Pod}; - -const TLP_READ_32: u8 = 0x00; -const TLP_READ_64: u8 = 0x20; - -const fn pack_bits4(first: u8, second: u8) -> u8 { - (first & ((1 << 4) - 1)) + ((second & ((1 << 4) - 1)) << 4) -} - -#[repr(C, align(1))] -#[derive(BitfieldStruct, Pod)] -pub struct TlpHeader { - #[bitfield(name = "len_tlps", ty = "libc::uint16_t", bits = "0..=9")] - #[bitfield(name = "at", ty = "libc::uint16_t", bits = "10..=11")] - #[bitfield(name = "attr", ty = "libc::uint16_t", bits = "12..=13")] - #[bitfield(name = "ep", ty = "libc::uint16_t", bits = "14..=14")] - #[bitfield(name = "td", ty = "libc::uint16_t", bits = "15..=15")] - #[bitfield(name = "r1", ty = "libc::uint8_t", bits = "16..=19")] - #[bitfield(name = "tc", ty = "libc::uint8_t", bits = "20..=22")] - #[bitfield(name = "r2", ty = "libc::uint8_t", bits = "23..=23")] - #[bitfield(name = "ty", ty = "libc::uint8_t", bits = "24..=31")] - buffer: [u8; 4], -} -const _: [(); core::mem::size_of::()] = [(); 4]; - -impl TlpHeader { - pub fn new(ty: u8, len_tlps: u16) -> Self { - let mut h = Self::zeroed(); - h.set_ty(ty); - if len_tlps < 0x1000 { - // shift length - h.set_len_tlps(len_tlps / 4); - } else { - // max length - h.set_len_tlps(len_tlps); - } - h - } -} - -#[repr(C)] -#[derive(Pod)] -pub struct TlpReadWrite32 { - header: TlpHeader, - be: u8, - tag: u8, - requester_id: u16, - address: u32, -} -const _: [(); core::mem::size_of::()] = [(); 0xC]; - -#[allow(unused)] -impl TlpReadWrite32 { - pub fn new_read(address: u32, len: u16, tag: u8, requester_id: u16) -> Self { - Self { - header: TlpHeader::new(TLP_READ_32, len), - be: pack_bits4(0xF, 0xF), - tag, - requester_id, - address, - } - } - - pub fn set_be(&mut self, first: u8, second: u8) { - self.be = pack_bits4(first, second); - } - - pub fn set_tag(&mut self, tag: u8) { - self.tag = tag; - } - - pub fn set_requester_id(&mut self, id: u16) { - self.requester_id = id; - } - - pub fn set_address(&mut self, address: u32) { - self.address = address; - } -} - -#[repr(C)] -#[derive(Pod)] -pub struct TlpReadWrite64 { - header: TlpHeader, - be: u8, - tag: u8, - requester_id: u16, - address_high: u32, - address_low: u32, -} -const _: [(); core::mem::size_of::()] = [(); 0x10]; - -#[allow(unused)] -impl TlpReadWrite64 { - pub fn new_read(address: u64, len: u16, tag: u8, requester_id: u16) -> Self { - Self { - header: TlpHeader::new(TLP_READ_64, len), - be: pack_bits4(0xF, 0xF), - tag, - requester_id, - address_high: (address >> 32) as u32, - address_low: address as u32, - } - } - - pub fn set_be(&mut self, first: u8, second: u8) { - self.be = pack_bits4(first, second); - } - - pub fn set_tag(&mut self, tag: u8) { - self.tag = tag; - } - - pub fn set_requester_id(&mut self, id: u16) { - self.requester_id = id; - } - - pub fn set_address(&mut self, address: u64) { - self.address_high = (address >> 32) as u32; - self.address_low = address as u32; - } -} - -/// Tlp Packet - Completion with Data -#[repr(C, align(1))] -#[derive(BitfieldStruct, Pod)] -pub struct TlpCplD { - header: TlpHeader, - #[bitfield(name = "byte_count", ty = "libc::uint16_t", bits = "0..=11")] - #[bitfield(name = "attr", ty = "libc::uint16_t", bits = "12..=12")] - #[bitfield(name = "ep", ty = "libc::uint16_t", bits = "13..=15")] - buffer1: [u8; 2], - completer_id: u16, - #[bitfield(name = "lower_addr", ty = "libc::uint8_t", bits = "0..=6")] - #[bitfield(name = "r1", ty = "libc::uint8_t", bits = "7..=7")] - buffer2: [u8; 1], - tag: u8, - requester_id: u16, -} -//const _: [(); core::mem::size_of::()] = [(); 0x10]; - -#[cfg(test)] -mod tests { - use super::{pack_bits4, TlpHeader, TlpReadWrite32, TlpReadWrite64, TLP_READ_32, TLP_READ_64}; - use dataview::Pod; - use memflow::size; - - #[test] - fn test_pack_bits4() { - assert_eq!(pack_bits4(0xA, 0xB), 0xBA); - assert_eq!(pack_bits4(0xAB, 0xCD), 0xDB); - } - - #[test] - fn test_header32() { - let header = TlpHeader::new(TLP_READ_32, 0x123); - assert_eq!(header.as_bytes(), &[72, 0, 0, 0]) - } - - #[test] - fn test_header64() { - let header = TlpHeader::new(TLP_READ_64, 0x123); - assert_eq!(header.as_bytes(), &[72, 0, 0, 32]) - } - - #[test] - fn test_tlp_rw32() { - let tlp = TlpReadWrite32::new_read(0x6000, 0x123, 0x80, 17); - assert_eq!(tlp.as_bytes(), &[72, 0, 0, 0, 255, 128, 17, 0, 0, 96, 0, 0]) - } - - #[test] - fn test_tlp_rw64() { - let tlp = TlpReadWrite64::new_read(size::gb(4) as u64 + 0x6000, 0x123, 0x80, 17); - assert_eq!( - tlp.as_bytes(), - &[72, 0, 0, 32, 255, 128, 17, 0, 1, 0, 0, 0, 0, 96, 0, 0] - ) - } -} diff --git a/src/ft60x.rs b/src/ft60x.rs deleted file mode 100644 index 58a9658..0000000 --- a/src/ft60x.rs +++ /dev/null @@ -1,200 +0,0 @@ -/// This module provides a wrapper around libusb to communicate with a FT60x chip directly. -/// The main interface will be through the chip configuration and read/write pipe functions. -mod chip; -pub use chip::{ChannelConfig, FifoMode, OptionalFeatureSupport}; - -use rusb::{ - request_type, DeviceHandle, DeviceList, Direction, GlobalContext, Recipient, RequestType, -}; - -use core::mem::size_of; -use core::time::Duration; - -use log::{info, trace}; - -use memflow::error::{Error, Result}; - -use dataview::Pod; - -pub const FTDI_VENDOR_ID: u16 = 0x0403; -pub const FTDI_FT60X_PRODUCT_ID: u16 = 0x601f; - -// TODO: enum? -pub const FTDI_COMMUNICATION_INTERFACE: u8 = 0x00; -pub const FTDI_DATA_INTERFACE: u8 = 0x01; - -// TODO: enum? -pub const FTDI_ENDPOINT_SESSION_OUT: u8 = 0x01; -pub const FTDI_ENDPOINT_OUT: u8 = 0x02; -pub const FTDI_ENDPOINT_IN: u8 = 0x82; - -pub struct FT60x { - handle: DeviceHandle, -} - -impl FT60x { - /// Tries to open a usb connection to a FT60x chip connected via libusb. - // TODO: handle multiple devices at the same time - pub fn new() -> Result { - let (dev, desc) = DeviceList::new() - .map_err(|_| Error::Connector("unable to get usb device list"))? - .iter() - .filter_map(|dev| match dev.device_descriptor() { - Ok(desc) => Some((dev, desc)), - Err(_) => None, - }) - .find(|(_dev, desc)| { - desc.vendor_id() == FTDI_VENDOR_ID && desc.product_id() == FTDI_FT60X_PRODUCT_ID - }) - .ok_or_else(|| Error::Connector("unable to find ftdi device"))?; - - info!( - "found FTDI device: {}:{} (bus {}, device {})", - desc.vendor_id(), - desc.product_id(), - dev.bus_number(), - dev.address() - ); - - // open handle and reset chip - let mut handle = dev - .open() - .map_err(|_| Error::Connector("unable to open ftdi usb device"))?; - handle - .reset() - .map_err(|_| Error::Connector("unable to reset ftdi device"))?; - - /* - let manufacturer = handle - .read_string_descriptor_ascii(desc.manufacturer_string_index().unwrap_or_default()) - .map_err(|_| Error::Connector("unable to read ftdi manufacturer name"))?; - let product = handle - .read_string_descriptor_ascii(desc.product_string_index().unwrap_or_default()) - .map_err(|_| Error::Connector("unable to read ftdi product name"))?; - let serial = handle - .read_string_descriptor_ascii(desc.serial_number_string_index().unwrap_or_default()) - .map_err(|_| Error::Connector("unable to read ftdi serial number"))?; - info!( - "device: manufacturer={} product={} serial={}", - manufacturer, product, serial - ); - */ - - // check driver state - if handle - .kernel_driver_active(FTDI_COMMUNICATION_INTERFACE) - .map_err(|_| Error::Connector("ftdi driver check failed"))? - { - return Err(Error::Connector( - "ftdi driver is already active on FTDI_COMMUNICATION_INTERFACE", - )); - } - info!("ftdi driver is not active on FTDI_COMMUNICATION_INTERFACE"); - - if handle - .kernel_driver_active(FTDI_DATA_INTERFACE) - .map_err(|_| Error::Connector("ftdi driver check failed"))? - { - return Err(Error::Connector( - "ftdi driver is already active on FTDI_DATA_INTERFACE", - )); - } - info!("ftdi driver is not active on FTDI_DATA_INTERFACE"); - - // claim interfaces - handle - .claim_interface(FTDI_COMMUNICATION_INTERFACE) - .map_err(|_| Error::Connector("unable to claim FTDI_COMMUNICATION_INTERFACE"))?; - handle - .claim_interface(FTDI_DATA_INTERFACE) - .map_err(|_| Error::Connector("unable to claim FTDI_DATA_INTERFACE"))?; - - Ok(Self { handle }) - } - - pub fn abort_pipe(&mut self, pipe_id: u8) -> Result<()> { - // dummy function, only used for ftdi compat - trace!("abort_pipe: {}", pipe_id); - Ok(()) - } - - pub fn set_suspend_timeout(&mut self, timeout: Duration) -> Result<()> { - // dummy function, only used for ftdi compat - trace!("set_suspend_timeout: {:?}", timeout); - Ok(()) - } - - /// Retrieves the FT60x chip configuration - pub fn config(&mut self) -> Result { - let mut buf = vec![0u8; size_of::()]; - self.handle - .read_control( - request_type(Direction::In, RequestType::Vendor, Recipient::Device), - 0xCF, - 1, - 0, - &mut buf, - Duration::from_millis(1000), - ) - .map_err(|_| Error::Connector("unable to get ft60x config"))?; - - // dataview buf to struct - let view = buf.as_data_view(); - Ok(view.copy::(0)) - } - - /// Writes the FT60x chip configuration - pub fn set_config(&mut self, conf: &chip::Config) -> Result<()> { - let bytes = self - .handle - .write_control( - request_type(Direction::Out, RequestType::Vendor, Recipient::Device), - 0xCF, - 0, - 0, - conf.as_bytes(), - Duration::from_millis(1000), - ) - .map_err(|_| Error::Connector("unable to set ft60x config"))?; - if bytes == size_of::() { - Ok(()) - } else { - Err(Error::Connector("unable to set ft60x config")) - } - } - - /// Write to the ft60x chip - pub fn write_pipe(&mut self, data: &[u8]) -> Result<()> { - self.write_bulk_raw(FTDI_ENDPOINT_OUT, data) - } - - /// Read from the ft60x chip - pub fn read_pipe(&mut self, data: &mut [u8]) -> Result { - self.send_read_request(data.len() as u32)?; - self.handle - .read_bulk(FTDI_ENDPOINT_IN, data, Duration::from_millis(1000)) - .map_err(|_| Error::Connector("unable to read from ft60x")) - } - - /// Sends a ControlRequest to issue a read with a given size - fn send_read_request(&mut self, len: u32) -> Result<()> { - let req = chip::ControlRequest::new(1, FTDI_ENDPOINT_IN, 1, len); - self.write_bulk_raw(FTDI_ENDPOINT_SESSION_OUT, req.as_bytes()) - } - - /// Does a raw bulk write to the chip and validates the sent size - fn write_bulk_raw(&self, endpoint: u8, buf: &[u8]) -> Result<()> { - // TODO: customizable write_bulk timeout - let bytes = self - .handle - .write_bulk(endpoint, buf, Duration::from_millis(1000)) - .map_err(|_| Error::Connector("unable to write to ft60x"))?; - if bytes == buf.len() { - Ok(()) - } else { - Err(Error::Connector( - "unable to write the entire buffer to the ft60x", - )) - } - } -} diff --git a/src/ft60x/chip.rs b/src/ft60x/chip.rs deleted file mode 100644 index 88cac58..0000000 --- a/src/ft60x/chip.rs +++ /dev/null @@ -1,112 +0,0 @@ -use dataview::Pod; - -/// Chip configuration - FIFO Mode -#[allow(unused)] -pub enum FifoMode { - Mode245 = 0, - Mode600 = 1, - Max = 2, -} - -/// Chip configuration - Channel Configuration -#[allow(unused)] -pub enum ChannelConfig { - Config4 = 0, - Config2 = 1, - Config1 = 2, - Config1OutPipe = 3, - Config1InPipe = 4, - Max = 5, -} - -/// Chip configuration - Optional Feature Support -#[allow(unused)] -pub enum OptionalFeatureSupport { - DisableAll = 0, - EnableBatteryCharging = 1, - DisableCancelSessionUnderrun = 2, - EnableNotificationMessageInch1 = 4, - EnableNotificationMessageInch2 = 8, - EnableNotificationMessageInch3 = 0x10, - EnableNotificationMessageInch4 = 0x20, - EnableNotificationMessageInchAll = 0x3C, - DisableUnderrunInch1 = 0x1 << 6, - DisableUnderrunInch2 = 0x1 << 7, - DisableUnderrunInch3 = 0x1 << 8, - DisableUnderrunInch4 = 0x1 << 9, - DisableUnderrunInchAll = 0xF << 6, -} - -/// Chip configuration - Config structure -#[repr(C)] -#[derive(Clone, Pod)] -pub struct Config { - // Device Descriptor - pub vendor_id: i16, - pub product_id: i16, - - // String Descriptors - pub string_descriptors: [i8; 128], - - // Configuration Descriptor - reserved1: i8, - pub power_attributes: i8, - pub power_consumption: i16, - - // Data Transfer Configuration - reserved2: i8, - pub fifo_clock: i8, - pub fifo_mode: i8, - pub channel_config: i8, - - // Optional Feature Support - pub optional_feature_support: i16, - pub battery_charging_gpio_config: i8, - pub flash_eeprom_detection: i8, // Read-only - - // MSIO and GPIO Configuration - pub msio_control: u32, - pub gpio_control: u32, -} -const _: [(); core::mem::size_of::()] = [(); 0x98]; - -#[repr(C, packed)] -#[derive(Copy, Clone, Pod)] -pub struct ControlRequest { - pub idx: u32, - pub pipe: u8, - pub cmd: u8, - unknown1: u8, - unknown2: u8, - pub len: u32, - unknown3: u32, - unknown4: u32, -} -const _: [(); core::mem::size_of::()] = [(); 0x14]; - -impl ControlRequest { - pub fn new(idx: u32, pipe: u8, cmd: u8, len: u32) -> Self { - Self { - idx, - pipe, - cmd, - unknown1: 0, - unknown2: 0, - len, - unknown3: 0, - unknown4: 0, - } - } -} - -#[cfg(test)] -mod tests { - use super::*; - use core::mem::size_of; - - #[test] - fn test_struct_sizes() { - assert_eq!(size_of::(), 0x98); - assert_eq!(size_of::(), 0x14); - } -} diff --git a/src/lib.rs b/src/lib.rs deleted file mode 100644 index 71b0233..0000000 --- a/src/lib.rs +++ /dev/null @@ -1,161 +0,0 @@ -mod fpga; -mod ft60x; - -//TODO: move? -use fpga::tlps::*; - -use log::{info, warn}; - -use fpga::{PhyConfigRd, PhyConfigWr}; - -use memflow::connector::ConnectorArgs; -use memflow::*; -use memflow_derive::connector; - -#[derive(Debug)] -pub enum PcieGen { - Gen1 = 0, - Gen2 = 1, -} - -#[allow(unused)] -pub struct PciLeech { - device: fpga::Device, - - version_major: u8, - version_minor: u8, - fpga_id: u8, - device_id: u16, - - phy_wr: PhyConfigWr, - phy_rd: PhyConfigRd, -} - -impl PciLeech { - pub fn new() -> Result { - let mut device = fpga::Device::new()?; - device.clear_pipe()?; - - let version = device.read_version()?; - if version.0 != 4 { - return Err(Error::Connector("only pcileech 4.x devices are supported")); - } - - device.write_inactivity_timer()?; - - let device_id = device.read_devid()?; - if device_id.1 == 0 { - return Err(Error::Connector("fpga did not find a valid pcie device id")); - } - - let (wr, rd) = device.get_phy()?; - - device.print_registers().ok(); - - Ok(Self { - device, - - version_major: version.0, - version_minor: version.1, - fpga_id: device_id.0, - device_id: device_id.1, - - phy_wr: wr, - phy_rd: rd, - }) - } - - pub fn pcie_link_width(&self) -> u8 { - match self.phy_rd.pl_sel_lnk_width() { - 0 => 1, - 1 => 2, - 2 => 4, - 3 => 8, - _ => 0, // invalid - } - } - - pub fn pcie_gen(&self) -> PcieGen { - match self.phy_rd.pl_sel_lnk_rate() { - 0 => PcieGen::Gen1, - 1 => PcieGen::Gen2, - _ => panic!("invalid sel_lnk_rate"), - } - } - - pub fn set_pcie_gen(&mut self, gen: PcieGen) -> Result<()> { - let genb = gen as u8; - if genb == self.phy_rd.pl_sel_lnk_rate() { - info!("requested pcie gen already set."); - return Ok(()); - } - - if genb != 0 && self.phy_rd.pl_link_gen2_cap() == 0 { - warn!("pcie gen2 is not supported by the fpga configuration"); - return Err(Error::Connector( - "pcie gen2 is not supported by the fpga configuration", - )); - } - - // update config - self.phy_wr.set_pl_directed_link_auton(1); - self.phy_wr.set_pl_directed_link_speed(genb); - self.phy_wr.set_pl_directed_link_change(2); - self.device.set_phy_wr(&self.phy_wr)?; - - // poll config update - for _ in 0..32 { - if let Ok(rd) = self.device.get_phy_rd() { - if rd.pl_directed_change_done() == 1 { - info!("fpga changes successfully applied"); - self.phy_rd = rd; - break; - } - } - } - - // reset config - self.phy_wr.set_pl_directed_link_auton(0); - self.phy_wr.set_pl_directed_link_speed(0); - self.phy_wr.set_pl_directed_link_change(0); - self.device.set_phy_wr(&self.phy_wr)?; - - // update internal state - self.phy_wr = self.device.get_phy_wr()?; - self.phy_rd = self.device.get_phy_rd()?; - - Ok(()) - } - - // test read functions - pub fn test_read(&mut self) -> Result<()> { - // create read request - self.device.read_mem_into_raw(0x1000, 0x1000, self.device_id); - Ok(()) - } -} - -impl PhysicalMemory for PciLeech { - fn phys_read_raw_list(&mut self, _data: &mut [PhysicalReadData]) -> Result<()> { - Err(Error::Connector( - "memflow_pcileech::phys_read_iter not implemented", - )) - } - - fn phys_write_raw_list(&mut self, _data: &[PhysicalWriteData]) -> Result<()> { - Err(Error::Connector( - "memflow_pcileech::phys_write_iter not implemented", - )) - } - - fn metadata(&self) -> PhysicalMemoryMetadata { - panic!() - } -} - -// TODO: handle args properly -/// Creates a new Pcileech Connector instance. -#[connector(name = "pcileech")] -pub fn create_connector(_args: &ConnectorArgs) -> Result { - PciLeech::new() -}