From c098181407abe6720a32fb982b5980e2212bbeb8 Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Fri, 27 Nov 2020 23:14:10 +0100
Subject: [PATCH 01/24] Updated to next branch

---
 memflow-pcileech/Cargo.toml | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/memflow-pcileech/Cargo.toml b/memflow-pcileech/Cargo.toml
index 35bc00c..715cfe1 100644
--- a/memflow-pcileech/Cargo.toml
+++ b/memflow-pcileech/Cargo.toml
@@ -16,8 +16,7 @@ categories = [ "api-bindings", "memory-management", "os" ]
 crate-type = ["lib", "cdylib"]
 
 [dependencies]
-memflow = { version = "0.1", features = ["inventory", "serde_derive"] }
-memflow-derive = { version = "0.1" }
+memflow = { git = "https://github.com/memflow/memflow", branch = "next", features = ["inventory", "serde_derive"] }
 log = { version = "0.4", default-features = false }
 simple_logger = "1.0"
 leechcore-sys = { path = "../leechcore-sys" }

From 2a3f0b9c4d8d352c360f824632137ee32bc1cb52 Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Fri, 27 Nov 2020 23:24:56 +0100
Subject: [PATCH 02/24] Updated to next branch

---
 leechcore-sys/src/lib.rs               | 1 +
 memflow-pcileech/Cargo.toml            | 2 +-
 memflow-pcileech/examples/read_phys.rs | 2 +-
 memflow-pcileech/src/lib.rs            | 7 ++++---
 4 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/leechcore-sys/src/lib.rs b/leechcore-sys/src/lib.rs
index 437f6a6..3d7e63d 100644
--- a/leechcore-sys/src/lib.rs
+++ b/leechcore-sys/src/lib.rs
@@ -3,6 +3,7 @@
 #![allow(non_camel_case_types)]
 #![allow(improper_ctypes)]
 #![allow(clippy::missing_safety_doc)]
+#![allow(clippy::redundant_static_lifetimes)]
 
 include!(concat!(env!("OUT_DIR"), "/leechcore.rs"));
 
diff --git a/memflow-pcileech/Cargo.toml b/memflow-pcileech/Cargo.toml
index 715cfe1..05604ca 100644
--- a/memflow-pcileech/Cargo.toml
+++ b/memflow-pcileech/Cargo.toml
@@ -16,7 +16,7 @@ categories = [ "api-bindings", "memory-management", "os" ]
 crate-type = ["lib", "cdylib"]
 
 [dependencies]
-memflow = { git = "https://github.com/memflow/memflow", branch = "next", features = ["inventory", "serde_derive"] }
+memflow = { git = "https://github.com/memflow/memflow", branch = "next", features = ["inventory", "memmapfiles"] }
 log = { version = "0.4", default-features = false }
 simple_logger = "1.0"
 leechcore-sys = { path = "../leechcore-sys" }
diff --git a/memflow-pcileech/examples/read_phys.rs b/memflow-pcileech/examples/read_phys.rs
index 8c4caf1..cfd09fc 100644
--- a/memflow-pcileech/examples/read_phys.rs
+++ b/memflow-pcileech/examples/read_phys.rs
@@ -3,7 +3,7 @@ use std::time::Instant;
 
 use log::{info, Level};
 
-use memflow::*;
+use memflow::prelude::v1::*;
 
 fn main() {
     simple_logger::SimpleLogger::new()
diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index 0ad9af9..123b2f5 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -9,8 +9,8 @@ use std::sync::{Arc, Mutex};
 
 use log::{error, info};
 
-use memflow::*;
-use memflow_derive::connector;
+use memflow::prelude::v1::*;
+use memflow::derive::connector;
 
 use leechcore_sys::*;
 
@@ -66,6 +66,7 @@ impl Clone for PciLeech {
 }
 
 // TODO: proper drop + free impl -> LcMemFree(pLcErrorInfo);
+#[allow(clippy::mutex_atomic)]
 impl PciLeech {
     pub fn new(device: &str) -> Result<Self> {
         Self::with_mapping(device, MemoryMap::new())
@@ -337,7 +338,7 @@ impl PhysicalMemory for PciLeech {
 }
 
 /// Creates a new PciLeech Connector instance.
-#[connector(name = "pcileech")]
+#[connector(name = "pcileech", ty = " PciLeech")]
 pub fn create_connector(args: &ConnectorArgs) -> Result<PciLeech> {
     let device = args
         .get("device")

From eb96015364404d7f79fc75fc6b2673b9688c0fec Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Fri, 27 Nov 2020 23:25:45 +0100
Subject: [PATCH 03/24] Fixed typo

---
 memflow-pcileech/src/lib.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index 123b2f5..083abba 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -338,7 +338,7 @@ impl PhysicalMemory for PciLeech {
 }
 
 /// Creates a new PciLeech Connector instance.
-#[connector(name = "pcileech", ty = " PciLeech")]
+#[connector(name = "pcileech", ty = "PciLeech")]
 pub fn create_connector(args: &ConnectorArgs) -> Result<PciLeech> {
     let device = args
         .get("device")

From b18c90689c8ae6b886654d0679f3bd51eb205add Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Fri, 27 Nov 2020 23:28:09 +0100
Subject: [PATCH 04/24] Fixed merge issue

---
 memflow-pcileech/examples/read_phys.rs |  2 +-
 memflow-pcileech/src/lib.rs            | 11 ++++++++---
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/memflow-pcileech/examples/read_phys.rs b/memflow-pcileech/examples/read_phys.rs
index cfd09fc..179b2d2 100644
--- a/memflow-pcileech/examples/read_phys.rs
+++ b/memflow-pcileech/examples/read_phys.rs
@@ -18,7 +18,7 @@ fn main() {
         ConnectorArgs::new()
     };
 
-    let mut conn = memflow_pcileech::create_connector(&conn_args)
+    let mut conn = memflow_pcileech::create_connector(Level::Debug, &conn_args)
         .expect("unable to initialize memflow_pcileech");
 
     let mut mem = vec![0; 8];
diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index 083abba..5470626 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -7,10 +7,10 @@ use std::ptr;
 use std::slice;
 use std::sync::{Arc, Mutex};
 
-use log::{error, info};
+use log::{error, info, Level};
 
-use memflow::prelude::v1::*;
 use memflow::derive::connector;
+use memflow::prelude::v1::*;
 
 use leechcore_sys::*;
 
@@ -339,7 +339,12 @@ impl PhysicalMemory for PciLeech {
 
 /// Creates a new PciLeech Connector instance.
 #[connector(name = "pcileech", ty = "PciLeech")]
-pub fn create_connector(args: &ConnectorArgs) -> Result<PciLeech> {
+pub fn create_connector(log_level: Level, args: &ConnectorArgs) -> Result<PciLeech> {
+    simple_logger::SimpleLogger::new()
+        .with_level(log_level.to_level_filter())
+        .init()
+        .ok();
+
     let device = args
         .get("device")
         .or_else(|| args.get_default())

From 96cb38b6aec6c6828ebe64cab4f4556d4694b90a Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Sun, 29 Nov 2020 17:22:07 +0100
Subject: [PATCH 05/24] Updated readme

---
 README.md | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/README.md b/README.md
index d908948..3b05d48 100644
--- a/README.md
+++ b/README.md
@@ -105,6 +105,12 @@ real_base=0x3000
 
 The `real_base` parameter is optional. If it is not set there will be no re-mapping.
 
+## Troubleshooting
+
+Q: The plugin is not detected/found by memflow
+
+A: Make sure to compile the plugin with the correct flags. More information can be found in the (usage)[#using-the-library-in-a-rust-project] section.
+
 ## License
 
 Licensed under GPL-3.0 License, see [LICENSE](LICENSE).

From c26521001ca912d7fc1a378ccb8035501c2b4032 Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Sun, 29 Nov 2020 17:23:00 +0100
Subject: [PATCH 06/24] Fixed readme formatting

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 3b05d48..50a68a9 100644
--- a/README.md
+++ b/README.md
@@ -109,7 +109,7 @@ The `real_base` parameter is optional. If it is not set there will be no re-mapp
 
 Q: The plugin is not detected/found by memflow
 
-A: Make sure to compile the plugin with the correct flags. More information can be found in the (usage)[#using-the-library-in-a-rust-project] section.
+A: Make sure to compile the plugin with the correct flags. See the [usage section](#using-the-library-in-a-rust-project) for more information.
 
 ## License
 

From 2eb3ca73e6f3290036f1676bd62f21d0b0600c6a Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Fri, 16 Apr 2021 17:59:05 +0200
Subject: [PATCH 07/24] Updated to latest memflow, added set_mem_map support

---
 memflow-pcileech/Cargo.toml               | 14 +++++-
 memflow-pcileech/examples/ps_inventory.rs | 57 +++++++++++++++++++++
 memflow-pcileech/examples/ps_win32.rs     | 56 +++++++++++++++++++++
 memflow-pcileech/examples/read_phys.rs    | 30 ++++++------
 memflow-pcileech/src/lib.rs               | 60 +++++++++++++++++------
 5 files changed, 188 insertions(+), 29 deletions(-)
 create mode 100644 memflow-pcileech/examples/ps_inventory.rs
 create mode 100644 memflow-pcileech/examples/ps_win32.rs

diff --git a/memflow-pcileech/Cargo.toml b/memflow-pcileech/Cargo.toml
index 82e34e2..35fde2c 100644
--- a/memflow-pcileech/Cargo.toml
+++ b/memflow-pcileech/Cargo.toml
@@ -16,11 +16,15 @@ categories = [ "api-bindings", "memory-management", "os" ]
 crate-type = ["lib", "cdylib"]
 
 [dependencies]
-memflow = { git = "https://github.com/memflow/memflow", branch = "next", features = ["inventory", "memmapfiles"] }
+memflow = { git = "https://github.com/memflow/memflow", branch = "next", features = ["plugins", "memmapfiles"] }
 log = { version = "0.4", default-features = false }
 simple_logger = "1.0"
 leechcore-sys = { path = "../leechcore-sys" }
 
+[dev-dependencies]
+clap = "2.33"
+memflow-win32 = { git = "https://github.com/memflow/memflow", branch = "next" }
+
 [features]
 default = []
 inventory = []
@@ -28,3 +32,11 @@ inventory = []
 [[example]]
 name = "read_phys"
 path = "examples/read_phys.rs"
+
+[[example]]
+name = "ps_win32"
+path = "examples/ps_win32.rs"
+
+[[example]]
+name = "ps_inventory"
+path = "examples/ps_inventory.rs"
diff --git a/memflow-pcileech/examples/ps_inventory.rs b/memflow-pcileech/examples/ps_inventory.rs
new file mode 100644
index 0000000..b1caab4
--- /dev/null
+++ b/memflow-pcileech/examples/ps_inventory.rs
@@ -0,0 +1,57 @@
+/*!
+This example shows how to use the pcileech connector in conjunction
+with a specific OS layer. This example uses the `Inventory` feature of memflow
+to create the connector itself and the os instance.
+
+The example is an adaption of the memflow core process list example:
+https://github.com/memflow/memflow/blob/next/memflow/examples/process_list.rs
+
+# Remarks:
+To run this example you must have the `pcileech` connector and `win32` plugin installed on your system.
+Make sure they can be found in one of the following locations:
+
+~/.local/lib/memflow/
+/usr/lib/memflow/
+
+or in any other path found in the official memflow documentation.
+*/
+use std::env::args;
+
+use log::{info, Level};
+
+use memflow::prelude::v1::*;
+
+fn main() {
+    simple_logger::SimpleLogger::new()
+        .with_level(Level::Debug.to_level_filter())
+        .init()
+        .unwrap();
+
+    let connector_args = if let Some(arg) = args().nth(1) {
+        Args::parse(arg.as_ref()).expect("unable to parse command line arguments")
+    } else {
+        Args::default()
+    };
+
+    let inventory = Inventory::scan();
+    let connector = inventory
+        .create_connector("pcileech", None, &connector_args)
+        .expect("unable to create pcileech connector");
+    let mut os = inventory
+        .create_os("win32", Some(connector), &Args::default())
+        .expect("unable to create win32 instance with pcileech connector");
+
+    let process_list = os.process_info_list().expect("unable to read process list");
+
+    info!(
+        "{:>5} {:>10} {:>10} {:<}",
+        "PID", "SYS ARCH", "PROC ARCH", "NAME"
+    );
+
+    for p in process_list {
+        info!(
+            "{:>5} {:^10} {:^10} {}",
+            p.pid, p.sys_arch, p.proc_arch, p.name
+        );
+    }
+}
diff --git a/memflow-pcileech/examples/ps_win32.rs b/memflow-pcileech/examples/ps_win32.rs
new file mode 100644
index 0000000..96f78e7
--- /dev/null
+++ b/memflow-pcileech/examples/ps_win32.rs
@@ -0,0 +1,56 @@
+/*!
+This example shows how to use the pcileech connector in conjunction
+with a specific OS layer. This example does not use the `Inventory` feature of memflow
+but hard-wires the connector instance with the OS layer directly.
+
+The example is an adaption of the memflow core process list example:
+https://github.com/memflow/memflow/blob/next/memflow/examples/process_list.rs
+
+# Remarks:
+The most flexible and recommended way to use memflow is to go through the inventory.
+The inventory allows the user to swap out connectors and os layers at runtime.
+For more information about the Inventory see the ps_inventory.rs example in this repository
+or check out the documentation at:
+https://docs.rs/memflow/0.1.5/memflow/connector/inventory/index.html
+*/
+use std::env::args;
+
+use log::{info, Level};
+
+use memflow::prelude::v1::*;
+use memflow_win32::prelude::v1::*;
+
+fn main() {
+    simple_logger::SimpleLogger::new()
+        .with_level(Level::Debug.to_level_filter())
+        .init()
+        .unwrap();
+
+    let connector_args = if let Some(arg) = args().nth(1) {
+        Args::parse(arg.as_ref()).expect("unable to parse command line arguments")
+    } else {
+        Args::default()
+    };
+
+    let connector = memflow_pcileech::create_connector(&connector_args, Level::Debug)
+        .expect("unable to create pcileech connector");
+
+    let mut os = Win32Kernel::builder(connector)
+        .build_default_caches()
+        .build()
+        .expect("unable to create win32 instance with pcileech connector");
+
+    let process_list = os.process_info_list().expect("unable to read process list");
+
+    info!(
+        "{:>5} {:>10} {:>10} {:<}",
+        "PID", "SYS ARCH", "PROC ARCH", "NAME"
+    );
+
+    for p in process_list {
+        info!(
+            "{:>5} {:^10} {:^10} {}",
+            p.pid, p.sys_arch, p.proc_arch, p.name
+        );
+    }
+}
diff --git a/memflow-pcileech/examples/read_phys.rs b/memflow-pcileech/examples/read_phys.rs
index 179b2d2..1881051 100644
--- a/memflow-pcileech/examples/read_phys.rs
+++ b/memflow-pcileech/examples/read_phys.rs
@@ -1,4 +1,8 @@
-use std::env;
+/*!
+This example shows how to use the pcileech connector to read physical_memory
+from a target machine. It also evaluates the number of read cycles per second
+and prints them to stdout.
+*/
 use std::time::Instant;
 
 use log::{info, Level};
@@ -11,30 +15,28 @@ fn main() {
         .init()
         .unwrap();
 
-    let args: Vec<String> = env::args().collect();
-    let conn_args = if args.len() > 1 {
-        ConnectorArgs::parse(&args[1]).expect("unable to parse arguments")
-    } else {
-        ConnectorArgs::new()
-    };
+    let mut connector = memflow_pcileech::create_connector(&Args::default(), Level::Debug)
+        .expect("unable to create pcileech connector");
 
-    let mut conn = memflow_pcileech::create_connector(Level::Debug, &conn_args)
-        .expect("unable to initialize memflow_pcileech");
+    let metadata = connector.metadata();
+    info!("Received metadata: {:?}", metadata);
 
     let mut mem = vec![0; 8];
-    conn.phys_read_raw_into(Address::from(0x1000).into(), &mut mem)
-        .unwrap();
+    connector
+        .phys_read_raw_into(Address::from(0x1000).into(), &mut mem)
+        .expect("unable to read physical memory");
     info!("Received memory: {:?}", mem);
 
     let start = Instant::now();
     let mut counter = 0;
     loop {
         let mut buf = vec![0; 0x1000];
-        conn.phys_read_raw_into(Address::from(0x1000).into(), &mut buf)
-            .unwrap();
+        connector
+            .phys_read_raw_into(Address::from(0x1000).into(), &mut buf)
+            .expect("unable to read physical memory");
 
         counter += 1;
-        if (counter % 10000) == 0 {
+        if (counter % 10000000) == 0 {
             let elapsed = start.elapsed().as_millis() as f64;
             if elapsed > 0.0 {
                 info!("{} reads/sec", (f64::from(counter)) / elapsed * 1000.0);
diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index 30f9e3f..3f35008 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -93,7 +93,8 @@ impl PciLeech {
             // TODO: handle version error
             // TODO: handle special case of fUserInputRequest
             error!("leechcore error: {:?}", err);
-            return Err(Error::Connector("unable to create leechcore context"));
+            return Err(Error(ErrorOrigin::Connector, ErrorKind::Configuration)
+                .log_error("unable to create leechcore context"));
         }
 
         Ok(Self {
@@ -146,7 +147,8 @@ impl PhysicalMemory for PciLeech {
             )
         };
         if result != 1 {
-            return Err(Error::Connector("unable to allocate scatter buffer"));
+            return Err(Error(ErrorOrigin::Connector, ErrorKind::InvalidMemorySize)
+                .log_error("unable to allocate scatter buffer"));
         }
 
         // prepare mems
@@ -243,7 +245,8 @@ impl PhysicalMemory for PciLeech {
             )
         };
         if result != 1 {
-            return Err(Error::Connector("unable to allocate scatter buffer"));
+            return Err(Error(ErrorOrigin::Connector, ErrorKind::InvalidMemorySize)
+                .log_error("unable to allocate scatter buffer"));
         }
 
         // prepare mems
@@ -337,24 +340,53 @@ impl PhysicalMemory for PciLeech {
     fn metadata(&self) -> PhysicalMemoryMetadata {
         self.metadata
     }
+
+    fn set_mem_map(&mut self, mem_map: MemoryMap<(Address, usize)>) {
+        // TODO: check if current mem_map is empty
+        // TODO: update metadata.size
+        self.mem_map = mem_map;
+    }
 }
 
 /// Creates a new PciLeech Connector instance.
-#[connector(name = "pcileech", ty = "PciLeech")]
-pub fn create_connector(log_level: Level, args: &ConnectorArgs) -> Result<PciLeech> {
+pub fn create_connector(args: &Args, log_level: Level) -> Result<PciLeech> {
     simple_logger::SimpleLogger::new()
         .with_level(log_level.to_level_filter())
         .init()
         .ok();
 
-    let device = args
-        .get("device")
-        .or_else(|| args.get_default())
-        .ok_or(Error::Connector("argument 'device' missing"))?;
-
-    if let Some(memmap) = args.get("memmap") {
-        PciLeech::with_memmap(device, memmap)
-    } else {
-        PciLeech::new(device)
+    let validator = ArgsValidator::new()
+        .arg(ArgDescriptor::new("default").description("the target device to be used by LeechCore"))
+        .arg(ArgDescriptor::new("device").description("the target device to be used by LeechCore"))
+        .arg(ArgDescriptor::new("memmap").description("the memory map file of the target machine"));
+
+    match validator.validate(&args) {
+        Ok(_) => {
+            let device = args.get("device").or_else(|| args.get_default()).ok_or(
+                Error(ErrorOrigin::Connector, ErrorKind::ArgValidation)
+                    .log_error("'device' argument is missing"),
+            )?;
+
+            if let Some(memmap) = args.get("memmap") {
+                PciLeech::with_memmap(device, memmap)
+            } else {
+                PciLeech::new(device)
+            }
+        }
+        Err(err) => {
+            error!(
+                "unable to validate provided arguments, valid arguments are:\n{}",
+                validator
+            );
+            Err(err)
+        }
     }
 }
+
+/// Creates a new PciLeech Connector instance.
+#[connector(name = "pcileech")]
+pub fn create_connector_instance(args: &Args, log_level: Level) -> Result<ConnectorInstance> {
+    let connector = create_connector(args, log_level)?;
+    let instance = ConnectorInstance::builder(connector).build();
+    Ok(instance)
+}

From eca56660a1b22f12f1c38c2db3ad102153eb91c8 Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Fri, 16 Apr 2021 19:00:20 +0200
Subject: [PATCH 08/24] Updated set_mem_map function to latest memflow/next

---
 memflow-pcileech/src/lib.rs | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index 3f35008..161ff56 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -342,9 +342,8 @@ impl PhysicalMemory for PciLeech {
     }
 
     fn set_mem_map(&mut self, mem_map: MemoryMap<(Address, usize)>) {
-        // TODO: check if current mem_map is empty
-        // TODO: update metadata.size
-        self.mem_map = mem_map;
+        self.metadata.size = mem_map.max_address().as_usize();
+        self.mem_map.merge(mem_map)
     }
 }
 

From 058f229d3cba53ff3d735f7f72cea0b19f057985 Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Fri, 16 Apr 2021 22:02:06 +0200
Subject: [PATCH 09/24] Updated to latest leechcore

---
 leechcore-sys/build.rs      |  5 +++--
 leechcore-sys/src/leechcore |  2 +-
 memflow-pcileech/src/lib.rs | 14 ++++++++------
 3 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/leechcore-sys/build.rs b/leechcore-sys/build.rs
index 8c8d32f..375063c 100644
--- a/leechcore-sys/build.rs
+++ b/leechcore-sys/build.rs
@@ -47,7 +47,8 @@ fn build_leechcore(target: &str) {
                 .map(|o| "src/leechcore/leechcore/".to_string() + o)
                 .collect::<Vec<_>>(),
         )
-        .flag(&format!("-D{}", os_define()));
+        .flag(&format!("-D{}", os_define()))
+        .flag("-D_GNU_SOURCE");
     // EXPORTED_FUNCTION= to not export any symbols
 
     if !target.contains("windows") {
@@ -105,7 +106,7 @@ fn main() {
 
     // generate bindings
     let mut builder = bindgen::builder()
-        .clang_arg(format!("-D{}", os_define()))
+        .clang_arg(format!("-D{} -D_GNU_SOURCE", os_define()))
         .header("./src/leechcore/leechcore/leechcore.h");
 
     // workaround for windows.h
diff --git a/leechcore-sys/src/leechcore b/leechcore-sys/src/leechcore
index e31a508..9968fa3 160000
--- a/leechcore-sys/src/leechcore
+++ b/leechcore-sys/src/leechcore
@@ -1 +1 @@
-Subproject commit e31a5084e264b4ab3c21238a95f703e994ec3384
+Subproject commit 9968fa3d88b3504c0ac68c582f111929afefd103
diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index 161ff56..df7abb8 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -92,9 +92,8 @@ impl PciLeech {
         if handle.is_null() {
             // TODO: handle version error
             // TODO: handle special case of fUserInputRequest
-            error!("leechcore error: {:?}", err);
             return Err(Error(ErrorOrigin::Connector, ErrorKind::Configuration)
-                .log_error("unable to create leechcore context"));
+                .log_error(&format!("unable to create leechcore context: {:?}", err)));
         }
 
         Ok(Self {
@@ -361,10 +360,13 @@ pub fn create_connector(args: &Args, log_level: Level) -> Result<PciLeech> {
 
     match validator.validate(&args) {
         Ok(_) => {
-            let device = args.get("device").or_else(|| args.get_default()).ok_or(
-                Error(ErrorOrigin::Connector, ErrorKind::ArgValidation)
-                    .log_error("'device' argument is missing"),
-            )?;
+            let device = args
+                .get("device")
+                .or_else(|| args.get_default())
+                .ok_or_else(|| {
+                    Error(ErrorOrigin::Connector, ErrorKind::ArgValidation)
+                        .log_error("'device' argument is missing")
+                })?;
 
             if let Some(memmap) = args.get("memmap") {
                 PciLeech::with_memmap(device, memmap)

From ee552a68ad0e9e3ed26e8e2a632d9763c19f0e3a Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Sat, 24 Apr 2021 23:19:09 +0200
Subject: [PATCH 10/24] Improved examples

---
 memflow-pcileech/examples/ps_inventory.rs | 2 +-
 memflow-pcileech/examples/ps_win32.rs     | 2 +-
 memflow-pcileech/examples/read_phys.rs    | 9 ++++++++-
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/memflow-pcileech/examples/ps_inventory.rs b/memflow-pcileech/examples/ps_inventory.rs
index b1caab4..1ccfd9f 100644
--- a/memflow-pcileech/examples/ps_inventory.rs
+++ b/memflow-pcileech/examples/ps_inventory.rs
@@ -30,7 +30,7 @@ fn main() {
     let connector_args = if let Some(arg) = args().nth(1) {
         Args::parse(arg.as_ref()).expect("unable to parse command line arguments")
     } else {
-        Args::default()
+        Args::new().insert("device", "FPGA")
     };
 
     let inventory = Inventory::scan();
diff --git a/memflow-pcileech/examples/ps_win32.rs b/memflow-pcileech/examples/ps_win32.rs
index 96f78e7..923030e 100644
--- a/memflow-pcileech/examples/ps_win32.rs
+++ b/memflow-pcileech/examples/ps_win32.rs
@@ -29,7 +29,7 @@ fn main() {
     let connector_args = if let Some(arg) = args().nth(1) {
         Args::parse(arg.as_ref()).expect("unable to parse command line arguments")
     } else {
-        Args::default()
+        Args::new().insert("device", "FPGA")
     };
 
     let connector = memflow_pcileech::create_connector(&connector_args, Level::Debug)
diff --git a/memflow-pcileech/examples/read_phys.rs b/memflow-pcileech/examples/read_phys.rs
index 1881051..62f6ca7 100644
--- a/memflow-pcileech/examples/read_phys.rs
+++ b/memflow-pcileech/examples/read_phys.rs
@@ -3,6 +3,7 @@ This example shows how to use the pcileech connector to read physical_memory
 from a target machine. It also evaluates the number of read cycles per second
 and prints them to stdout.
 */
+use std::env::args;
 use std::time::Instant;
 
 use log::{info, Level};
@@ -15,7 +16,13 @@ fn main() {
         .init()
         .unwrap();
 
-    let mut connector = memflow_pcileech::create_connector(&Args::default(), Level::Debug)
+    let connector_args = if let Some(arg) = args().nth(1) {
+        Args::parse(arg.as_ref()).expect("unable to parse command line arguments")
+    } else {
+        Args::new().insert("device", "FPGA")
+    };
+
+    let mut connector = memflow_pcileech::create_connector(&connector_args, Level::Debug)
         .expect("unable to create pcileech connector");
 
     let metadata = connector.metadata();

From be5ce8bc960105f7952f99567f425d65c7cbf6bc Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Mon, 22 Nov 2021 18:52:25 +0100
Subject: [PATCH 11/24] Ported to latest memflow/next

---
 leechcore-sys/src/leechcore |   2 +-
 memflow-pcileech/src/lib.rs | 161 +++++++++++++++++++++++-------------
 2 files changed, 103 insertions(+), 60 deletions(-)

diff --git a/leechcore-sys/src/leechcore b/leechcore-sys/src/leechcore
index 9968fa3..99b3bba 160000
--- a/leechcore-sys/src/leechcore
+++ b/leechcore-sys/src/leechcore
@@ -1 +1 @@
-Subproject commit 9968fa3d88b3504c0ac68c582f111929afefd103
+Subproject commit 99b3bba5ff04f1420ccea25e1f6907c7f4f3782c
diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index df7abb8..9ba1928 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -1,5 +1,3 @@
-// https://github.com/ufrisk/pcileech/blob/master/pcileech/device.c
-
 use std::ffi::c_void;
 use std::os::raw::c_char;
 use std::path::Path;
@@ -9,7 +7,8 @@ use std::sync::{Arc, Mutex};
 
 use log::{error, info, Level};
 
-use memflow::derive::connector;
+use memflow::cglue;
+use memflow::mem::phys_mem::*;
 use memflow::prelude::v1::*;
 
 use leechcore_sys::*;
@@ -20,6 +19,8 @@ const BUF_ALIGN: u64 = 4;
 const BUF_MIN_LEN: usize = 8;
 const BUF_LEN_ALIGN: usize = 8;
 
+cglue_impl_group!(PciLeech, ConnectorInstance<'a>, {});
+
 fn build_lc_config(device: &str) -> LC_CONFIG {
     let cdevice = unsafe { &*(device.as_bytes() as *const [u8] as *const [c_char]) };
     let mut adevice: [c_char; 260] = [0; 260];
@@ -51,7 +52,7 @@ const fn calc_num_pages(start: u64, size: u64) -> u64 {
 pub struct PciLeech {
     handle: Arc<Mutex<HANDLE>>,
     metadata: PhysicalMemoryMetadata,
-    mem_map: MemoryMap<(Address, usize)>,
+    mem_map: MemoryMap<(Address, umem)>,
 }
 
 unsafe impl Send for PciLeech {}
@@ -78,13 +79,13 @@ impl PciLeech {
             "loading memory mappings from file: {}",
             path.as_ref().to_string_lossy()
         );
-        let memmap = MemoryMap::open(path)?;
-        info!("{:?}", memmap);
-        Self::with_mapping(device, memmap)
+        let mem_map = MemoryMap::open(path)?;
+        info!("{:?}", mem_map);
+        Self::with_mapping(device, mem_map)
     }
 
     #[allow(clippy::mutex_atomic)]
-    fn with_mapping(device: &str, mem_map: MemoryMap<(Address, usize)>) -> Result<Self> {
+    fn with_mapping(device: &str, mem_map: MemoryMap<(Address, umem)>) -> Result<Self> {
         // open device
         let mut conf = build_lc_config(device);
         let err = std::ptr::null_mut::<PLC_CONFIG_ERRORINFO>();
@@ -96,12 +97,15 @@ impl PciLeech {
                 .log_error(&format!("unable to create leechcore context: {:?}", err)));
         }
 
+        // TODO: update mem_map max size here instead of setting up metadata from scratch?
+
         Ok(Self {
             handle: Arc::new(Mutex::new(handle)),
             metadata: PhysicalMemoryMetadata {
-                size: conf.paMax as usize,
+                max_address: (conf.paMax as usize - 1_usize).into(),
+                real_size: conf.paMax as umem,
                 readonly: conf.fVolatile == 0,
-                // TODO: writable flag
+                ideal_batch_size: 128,
             },
             mem_map,
         })
@@ -127,12 +131,21 @@ struct WriteGap {
 
 // TODO: handle mem_map
 impl PhysicalMemory for PciLeech {
-    fn phys_read_raw_list(&mut self, data: &mut [PhysicalReadData]) -> Result<()> {
-        //let mem_map = &self.mem_map;
+    fn phys_read_raw_iter<'a>(
+        &mut self,
+        data: CIterator<PhysicalReadData<'a>>,
+        out_fail: &mut PhysicalReadFailCallback<'_, 'a>,
+    ) -> Result<()> {
+        let mem_map = &self.mem_map;
+
+        let mut callback = &mut |(a, b): (Address, _)| out_fail.call(MemData(a.into(), b));
+        let vec = mem_map
+            .map_iter(data.map(|MemData(addr, buf)| (addr, buf)), &mut callback)
+            .collect::<Vec<_>>();
 
         // get total number of pages
-        let num_pages = data.iter().fold(0u64, |acc, read| {
-            acc + calc_num_pages(read.0.as_u64(), read.1.len() as u64)
+        let num_pages = vec.iter().fold(0u64, |acc, read| {
+            acc + calc_num_pages(read.0 .0.to_umem(), read.1.len() as u64)
         });
 
         // allocate scatter buffer
@@ -153,17 +166,17 @@ impl PhysicalMemory for PciLeech {
         // prepare mems
         let mut gaps = Vec::new();
         let mut i = 0usize;
-        for read in data.iter_mut() {
-            for (page_addr, out) in read.1.page_chunks(read.0.into(), PAGE_SIZE) {
+        for read in vec.into_iter() {
+            for (page_addr, out) in read.1.page_chunks(read.0 .0.into(), PAGE_SIZE) {
                 let mem = unsafe { *mems.add(i) };
 
-                let addr_align = page_addr.as_u64() & (BUF_ALIGN - 1);
+                let addr_align = page_addr.to_umem() & (BUF_ALIGN - 1);
                 let len_align = out.len() & (BUF_LEN_ALIGN - 1);
 
                 if addr_align == 0 && len_align == 0 && out.len() >= BUF_MIN_LEN {
                     // properly aligned read
-                    unsafe { (*mem).qwA = page_addr.as_u64() };
-                    unsafe { (*mem).pb = out.as_mut_ptr() };
+                    unsafe { (*mem).qwA = page_addr.to_umem() };
+                    unsafe { (*mem).__bindgen_anon_1.pb = out.as_mut_ptr() };
                     unsafe { (*mem).cb = out.len() as u32 };
                 } else {
                     // non-aligned or small read
@@ -181,8 +194,8 @@ impl PhysicalMemory for PciLeech {
                         out_end: out.len() + addr_align as usize,
                     });
 
-                    unsafe { (*mem).qwA = page_addr.as_u64() - addr_align };
-                    unsafe { (*mem).pb = buffer_ptr };
+                    unsafe { (*mem).qwA = page_addr.to_umem() - addr_align };
+                    unsafe { (*mem).__bindgen_anon_1.pb = buffer_ptr };
                     unsafe { (*mem).cb = buffer_len as u32 };
                 }
 
@@ -225,12 +238,21 @@ impl PhysicalMemory for PciLeech {
         Ok(())
     }
 
-    fn phys_write_raw_list(&mut self, data: &[PhysicalWriteData]) -> Result<()> {
-        //let mem_map = &self.mem_map;
+    fn phys_write_raw_iter<'a>(
+        &mut self,
+        data: CIterator<PhysicalWriteData<'a>>,
+        out_fail: &mut PhysicalWriteFailCallback<'_, 'a>,
+    ) -> Result<()> {
+        let mem_map = &self.mem_map;
+
+        let mut callback = &mut |(a, b): (Address, _)| out_fail.call(MemData(a.into(), b));
+        let vec = mem_map
+            .map_iter(data.map(|MemData(addr, buf)| (addr, buf)), &mut callback)
+            .collect::<Vec<_>>();
 
         // get total number of pages
-        let num_pages = data.iter().fold(0u64, |acc, read| {
-            acc + calc_num_pages(read.0.as_u64(), read.1.len() as u64)
+        let num_pages = vec.iter().fold(0u64, |acc, read| {
+            acc + calc_num_pages(read.0 .0.to_umem(), read.1.len() as u64)
         });
 
         // allocate scatter buffer
@@ -251,17 +273,17 @@ impl PhysicalMemory for PciLeech {
         // prepare mems
         let mut gaps = Vec::new();
         let mut i = 0usize;
-        for write in data.iter() {
-            for (page_addr, out) in write.1.page_chunks(write.0.into(), PAGE_SIZE) {
+        for write in vec.iter() {
+            for (page_addr, out) in write.1.page_chunks(write.0 .0.into(), PAGE_SIZE) {
                 let mem = unsafe { *mems.add(i) };
 
-                let addr_align = page_addr.as_u64() & (BUF_ALIGN - 1);
+                let addr_align = page_addr.to_umem() & (BUF_ALIGN - 1);
                 let len_align = out.len() & (BUF_LEN_ALIGN - 1);
 
                 if addr_align == 0 && len_align == 0 && out.len() >= BUF_MIN_LEN {
                     // properly aligned read
-                    unsafe { (*mem).qwA = page_addr.as_u64() };
-                    unsafe { (*mem).pb = out.as_ptr() as *mut u8 };
+                    unsafe { (*mem).qwA = page_addr.to_umem() };
+                    unsafe { (*mem).__bindgen_anon_1.pb = out.as_ptr() as *mut u8 };
                     unsafe { (*mem).cb = out.len() as u32 };
                 } else {
                     // non-aligned or small read
@@ -269,7 +291,7 @@ impl PhysicalMemory for PciLeech {
                     buffer_len += BUF_LEN_ALIGN - (buffer_len & (BUF_LEN_ALIGN - 1));
 
                     // prepare gap buffer for reading
-                    let write_addr = (page_addr.as_u64() - addr_align).into();
+                    let write_addr = (page_addr.to_umem() - addr_align).into();
                     let buffer = vec![0u8; buffer_len].into_boxed_slice();
                     let buffer_ptr = Box::into_raw(buffer) as *mut u8;
 
@@ -284,8 +306,8 @@ impl PhysicalMemory for PciLeech {
                     });
 
                     // store pointers into pcileech struct for writing (after we dispatched a read)
-                    unsafe { (*mem).qwA = write_addr.as_u64() };
-                    unsafe { (*mem).pb = buffer_ptr };
+                    unsafe { (*mem).qwA = write_addr.to_umem() };
+                    unsafe { (*mem).__bindgen_anon_1.pb = buffer_ptr };
                     unsafe { (*mem).cb = buffer_len as u32 };
                 }
 
@@ -295,18 +317,17 @@ impl PhysicalMemory for PciLeech {
 
         // dispatch necessary reads to fill the gaps
         if !gaps.is_empty() {
-            let mut datas = gaps
-                .iter()
-                .map(|g| {
-                    PhysicalReadData(g.gap_addr, unsafe {
-                        slice::from_raw_parts_mut(g.gap_buffer, g.gap_buffer_len)
-                    })
-                })
-                .collect::<Vec<_>>();
-
-            self.phys_read_raw_list(datas.as_mut_slice())?;
-
-            for (gap, read) in gaps.iter().zip(datas) {
+            let iter = gaps.iter().map(|g| {
+                MemData(
+                    g.gap_addr,
+                    unsafe { slice::from_raw_parts_mut(g.gap_buffer, g.gap_buffer_len) }.into(),
+                )
+            });
+
+            let out_fail = &mut |_| true;
+            self.phys_read_raw_iter((&mut iter.clone()).into(), &mut out_fail.into())?;
+
+            for (gap, mut read) in gaps.iter().zip(iter) {
                 let in_buffer =
                     unsafe { slice::from_raw_parts(gap.in_buffer, gap.in_end - gap.in_start) };
                 read.1[gap.in_start..gap.in_end].copy_from_slice(in_buffer);
@@ -340,24 +361,32 @@ impl PhysicalMemory for PciLeech {
         self.metadata
     }
 
-    fn set_mem_map(&mut self, mem_map: MemoryMap<(Address, usize)>) {
-        self.metadata.size = mem_map.max_address().as_usize();
-        self.mem_map.merge(mem_map)
+    fn set_mem_map(&mut self, mem_map: &[PhysicalMemoryMapping]) {
+        let map = MemoryMap::<(Address, umem)>::from_vec(mem_map.to_vec());
+        self.mem_map.merge(map);
+
+        // update metadata fields
+        self.metadata.max_address = self.mem_map.max_address();
+        self.metadata.real_size = self.mem_map.real_size();
     }
 }
 
+fn validator() -> ArgsValidator {
+    ArgsValidator::new()
+        .arg(ArgDescriptor::new("default").description("the target device to be used by LeechCore"))
+        .arg(ArgDescriptor::new("device").description("the target device to be used by LeechCore"))
+        .arg(ArgDescriptor::new("memmap").description("the memory map file of the target machine"))
+}
+
 /// Creates a new PciLeech Connector instance.
+#[connector(name = "pcileech", help_fn = "help", target_list_fn = "target_list")]
 pub fn create_connector(args: &Args, log_level: Level) -> Result<PciLeech> {
     simple_logger::SimpleLogger::new()
         .with_level(log_level.to_level_filter())
         .init()
         .ok();
 
-    let validator = ArgsValidator::new()
-        .arg(ArgDescriptor::new("default").description("the target device to be used by LeechCore"))
-        .arg(ArgDescriptor::new("device").description("the target device to be used by LeechCore"))
-        .arg(ArgDescriptor::new("memmap").description("the memory map file of the target machine"));
-
+    let validator = validator();
     match validator.validate(&args) {
         Ok(_) => {
             let device = args
@@ -384,10 +413,24 @@ pub fn create_connector(args: &Args, log_level: Level) -> Result<PciLeech> {
     }
 }
 
-/// Creates a new PciLeech Connector instance.
-#[connector(name = "pcileech")]
-pub fn create_connector_instance(args: &Args, log_level: Level) -> Result<ConnectorInstance> {
-    let connector = create_connector(args, log_level)?;
-    let instance = ConnectorInstance::builder(connector).build();
-    Ok(instance)
+/// Retrieve the help text for the Qemu Procfs Connector.
+pub fn help() -> String {
+    let validator = validator();
+    format!(
+        "\
+The `pcileech` connector implements the LeechCore interface of pcileech for memflow.
+
+More information about pcileech can be found under https://github.com/ufrisk/pcileech.
+
+This connector requires access to the usb ports to access the pcileech hardware.
+
+Available arguments are:
+{}",
+        validator.to_string()
+    )
+}
+
+/// Retrieve a list of all currently available PciLeech targets.
+pub fn target_list() -> Result<Vec<TargetInfo>> {
+    Ok(vec![])
 }

From 52773488a14ce204438f9b531fcac69f202345ed Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Mon, 22 Nov 2021 20:37:29 +0100
Subject: [PATCH 12/24] Fixed leechcore-sys compilation; Fixed examples

---
 README.md                              |  2 +-
 leechcore-sys/build.rs                 |  1 +
 memflow-pcileech/examples/read_phys.rs |  6 ++++--
 memflow-pcileech/src/lib.rs            | 12 +-----------
 4 files changed, 7 insertions(+), 14 deletions(-)

diff --git a/README.md b/README.md
index 5dfa18e..e918c2f 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,6 @@
 # memflow-pcileech
 
-This connector implements a rust-native implementation of the pcileech interface.
+This connector implements the [LeechCore](https://github.com/ufrisk/LeechCore) interface of pcileech for memflow.
 
 More information about pcileech can be found under https://github.com/ufrisk/pcileech.
 
diff --git a/leechcore-sys/build.rs b/leechcore-sys/build.rs
index 375063c..dbc6240 100644
--- a/leechcore-sys/build.rs
+++ b/leechcore-sys/build.rs
@@ -32,6 +32,7 @@ fn build_leechcore(target: &str) {
         "device_pmem.c",
         "device_tmd.c",
         "device_usb3380.c",
+        "device_vmware.c",
         "leechrpcclient.c",
     ];
     if target.contains("windows") {
diff --git a/memflow-pcileech/examples/read_phys.rs b/memflow-pcileech/examples/read_phys.rs
index 62f6ca7..1a09b00 100644
--- a/memflow-pcileech/examples/read_phys.rs
+++ b/memflow-pcileech/examples/read_phys.rs
@@ -30,7 +30,8 @@ fn main() {
 
     let mut mem = vec![0; 8];
     connector
-        .phys_read_raw_into(Address::from(0x1000).into(), &mut mem)
+        .phys_view()
+        .read_raw_into(Address::from(0x1000).into(), &mut mem)
         .expect("unable to read physical memory");
     info!("Received memory: {:?}", mem);
 
@@ -39,7 +40,8 @@ fn main() {
     loop {
         let mut buf = vec![0; 0x1000];
         connector
-            .phys_read_raw_into(Address::from(0x1000).into(), &mut buf)
+            .phys_view()
+            .read_raw_into(Address::from(0x1000).into(), &mut buf)
             .expect("unable to read physical memory");
 
         counter += 1;
diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index 9ba1928..05bf84d 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -48,7 +48,7 @@ const fn calc_num_pages(start: u64, size: u64) -> u64 {
 }
 
 #[allow(clippy::mutex_atomic)]
-#[derive(Debug)]
+#[derive(Clone, Debug)]
 pub struct PciLeech {
     handle: Arc<Mutex<HANDLE>>,
     metadata: PhysicalMemoryMetadata,
@@ -57,16 +57,6 @@ pub struct PciLeech {
 
 unsafe impl Send for PciLeech {}
 
-impl Clone for PciLeech {
-    fn clone(&self) -> Self {
-        Self {
-            handle: self.handle.clone(),
-            metadata: self.metadata,
-            mem_map: self.mem_map.clone(),
-        }
-    }
-}
-
 // TODO: proper drop + free impl -> LcMemFree(pLcErrorInfo);
 #[allow(clippy::mutex_atomic)]
 impl PciLeech {

From 80de3291580a74a59e74a77afc861ea55d25b272 Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Mon, 22 Nov 2021 21:14:37 +0000
Subject: [PATCH 13/24] Actually implemented memory mappings with optional
 override from the os

---
 memflow-pcileech/src/lib.rs | 90 +++++++++++++++++++++----------------
 1 file changed, 51 insertions(+), 39 deletions(-)

diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index 05bf84d..f951cae 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -48,11 +48,11 @@ const fn calc_num_pages(start: u64, size: u64) -> u64 {
 }
 
 #[allow(clippy::mutex_atomic)]
-#[derive(Clone, Debug)]
+#[derive(Clone)]
 pub struct PciLeech {
     handle: Arc<Mutex<HANDLE>>,
-    metadata: PhysicalMemoryMetadata,
-    mem_map: MemoryMap<(Address, umem)>,
+    conf: LC_CONFIG,
+    mem_map: Option<MemoryMap<(Address, umem)>>,
 }
 
 unsafe impl Send for PciLeech {}
@@ -61,21 +61,21 @@ unsafe impl Send for PciLeech {}
 #[allow(clippy::mutex_atomic)]
 impl PciLeech {
     pub fn new(device: &str) -> Result<Self> {
-        Self::with_mapping(device, MemoryMap::new())
+        Self::new_internal(device, None)
     }
 
-    pub fn with_memmap<P: AsRef<Path>>(device: &str, path: P) -> Result<Self> {
+    pub fn with_mem_map_file<P: AsRef<Path>>(device: &str, path: P) -> Result<Self> {
         info!(
             "loading memory mappings from file: {}",
             path.as_ref().to_string_lossy()
         );
         let mem_map = MemoryMap::open(path)?;
         info!("{:?}", mem_map);
-        Self::with_mapping(device, mem_map)
+        Self::new_internal(device, Some(mem_map))
     }
 
     #[allow(clippy::mutex_atomic)]
-    fn with_mapping(device: &str, mem_map: MemoryMap<(Address, umem)>) -> Result<Self> {
+    fn new_internal(device: &str, mem_map: Option<MemoryMap<(Address, umem)>>) -> Result<Self> {
         // open device
         let mut conf = build_lc_config(device);
         let err = std::ptr::null_mut::<PLC_CONFIG_ERRORINFO>();
@@ -87,16 +87,9 @@ impl PciLeech {
                 .log_error(&format!("unable to create leechcore context: {:?}", err)));
         }
 
-        // TODO: update mem_map max size here instead of setting up metadata from scratch?
-
         Ok(Self {
             handle: Arc::new(Mutex::new(handle)),
-            metadata: PhysicalMemoryMetadata {
-                max_address: (conf.paMax as usize - 1_usize).into(),
-                real_size: conf.paMax as umem,
-                readonly: conf.fVolatile == 0,
-                ideal_batch_size: 128,
-            },
+            conf,
             mem_map,
         })
     }
@@ -126,16 +119,20 @@ impl PhysicalMemory for PciLeech {
         data: CIterator<PhysicalReadData<'a>>,
         out_fail: &mut PhysicalReadFailCallback<'_, 'a>,
     ) -> Result<()> {
-        let mem_map = &self.mem_map;
-
-        let mut callback = &mut |(a, b): (Address, _)| out_fail.call(MemData(a.into(), b));
-        let vec = mem_map
-            .map_iter(data.map(|MemData(addr, buf)| (addr, buf)), &mut callback)
-            .collect::<Vec<_>>();
+        let vec = if let Some(mem_map) = &self.mem_map {
+            let mut callback = &mut |(a, b): (Address, _)| out_fail.call(MemData(a.into(), b));
+            mem_map
+                .map_iter(data.map(|MemData(addr, buf)| (addr, buf)), &mut callback)
+                .map(|d| (d.0 .0.into(), d.1))
+                .collect::<Vec<_>>()
+        } else {
+            data.map(|MemData(addr, buf)| (addr, buf))
+                .collect::<Vec<_>>()
+        };
 
         // get total number of pages
         let num_pages = vec.iter().fold(0u64, |acc, read| {
-            acc + calc_num_pages(read.0 .0.to_umem(), read.1.len() as u64)
+            acc + calc_num_pages(read.0.to_umem(), read.1.len() as u64)
         });
 
         // allocate scatter buffer
@@ -157,7 +154,7 @@ impl PhysicalMemory for PciLeech {
         let mut gaps = Vec::new();
         let mut i = 0usize;
         for read in vec.into_iter() {
-            for (page_addr, out) in read.1.page_chunks(read.0 .0.into(), PAGE_SIZE) {
+            for (page_addr, out) in read.1.page_chunks(read.0.into(), PAGE_SIZE) {
                 let mem = unsafe { *mems.add(i) };
 
                 let addr_align = page_addr.to_umem() & (BUF_ALIGN - 1);
@@ -233,16 +230,20 @@ impl PhysicalMemory for PciLeech {
         data: CIterator<PhysicalWriteData<'a>>,
         out_fail: &mut PhysicalWriteFailCallback<'_, 'a>,
     ) -> Result<()> {
-        let mem_map = &self.mem_map;
-
-        let mut callback = &mut |(a, b): (Address, _)| out_fail.call(MemData(a.into(), b));
-        let vec = mem_map
-            .map_iter(data.map(|MemData(addr, buf)| (addr, buf)), &mut callback)
-            .collect::<Vec<_>>();
+        let vec = if let Some(mem_map) = &self.mem_map {
+            let mut callback = &mut |(a, b): (Address, _)| out_fail.call(MemData(a.into(), b));
+            mem_map
+                .map_iter(data.map(|MemData(addr, buf)| (addr, buf)), &mut callback)
+                .map(|d| (d.0 .0.into(), d.1))
+                .collect::<Vec<_>>()
+        } else {
+            data.map(|MemData(addr, buf)| (addr, buf))
+                .collect::<Vec<_>>()
+        };
 
         // get total number of pages
         let num_pages = vec.iter().fold(0u64, |acc, read| {
-            acc + calc_num_pages(read.0 .0.to_umem(), read.1.len() as u64)
+            acc + calc_num_pages(read.0.to_umem(), read.1.len() as u64)
         });
 
         // allocate scatter buffer
@@ -264,7 +265,7 @@ impl PhysicalMemory for PciLeech {
         let mut gaps = Vec::new();
         let mut i = 0usize;
         for write in vec.iter() {
-            for (page_addr, out) in write.1.page_chunks(write.0 .0.into(), PAGE_SIZE) {
+            for (page_addr, out) in write.1.page_chunks(write.0.into(), PAGE_SIZE) {
                 let mem = unsafe { *mems.add(i) };
 
                 let addr_align = page_addr.to_umem() & (BUF_ALIGN - 1);
@@ -348,16 +349,27 @@ impl PhysicalMemory for PciLeech {
     }
 
     fn metadata(&self) -> PhysicalMemoryMetadata {
-        self.metadata
+        let (max_address, real_size) = if let Some(mem_map) = &self.mem_map {
+            (mem_map.max_address(), mem_map.real_size())
+        } else {
+            (
+                (self.conf.paMax as usize - 1_usize).into(),
+                self.conf.paMax as umem,
+            )
+        };
+        PhysicalMemoryMetadata {
+            max_address,
+            real_size,
+            readonly: self.conf.fVolatile == 0,
+            ideal_batch_size: 128,
+        }
     }
 
+    // Sets the memory map only in cases where no previous memory map was being set by the end-user.
     fn set_mem_map(&mut self, mem_map: &[PhysicalMemoryMapping]) {
-        let map = MemoryMap::<(Address, umem)>::from_vec(mem_map.to_vec());
-        self.mem_map.merge(map);
-
-        // update metadata fields
-        self.metadata.max_address = self.mem_map.max_address();
-        self.metadata.real_size = self.mem_map.real_size();
+        if self.mem_map.is_none() {
+            self.mem_map = Some(MemoryMap::<(Address, umem)>::from_vec(mem_map.to_vec()));
+        }
     }
 }
 
@@ -388,7 +400,7 @@ pub fn create_connector(args: &Args, log_level: Level) -> Result<PciLeech> {
                 })?;
 
             if let Some(memmap) = args.get("memmap") {
-                PciLeech::with_memmap(device, memmap)
+                PciLeech::with_mem_map_file(device, memmap)
             } else {
                 PciLeech::new(device)
             }

From 1f778420866eb5a3da8a16808edb4bf79a173076 Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Mon, 22 Nov 2021 21:29:49 +0000
Subject: [PATCH 14/24] Fixed gap write handling when additional reads are
 required

---
 memflow-pcileech/src/lib.rs | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index f951cae..e3e17ea 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -308,17 +308,25 @@ impl PhysicalMemory for PciLeech {
 
         // dispatch necessary reads to fill the gaps
         if !gaps.is_empty() {
-            let iter = gaps.iter().map(|g| {
-                MemData(
-                    g.gap_addr,
-                    unsafe { slice::from_raw_parts_mut(g.gap_buffer, g.gap_buffer_len) }.into(),
-                )
-            });
+            let mut vec = gaps
+                .iter()
+                .map(|g| {
+                    MemData(
+                        g.gap_addr,
+                        unsafe { slice::from_raw_parts_mut(g.gap_buffer, g.gap_buffer_len) }.into(),
+                    )
+                })
+                .collect::<Vec<_>>();
+
+            let mut iter = vec
+                .iter_mut()
+                .map(|MemData(a, d): &mut PhysicalReadData| MemData(*a, d.into()));
 
             let out_fail = &mut |_| true;
-            self.phys_read_raw_iter((&mut iter.clone()).into(), &mut out_fail.into())?;
 
-            for (gap, mut read) in gaps.iter().zip(iter) {
+            self.phys_read_raw_iter((&mut iter).into(), &mut out_fail.into())?;
+
+            for (gap, mut read) in gaps.iter().zip(vec) {
                 let in_buffer =
                     unsafe { slice::from_raw_parts(gap.in_buffer, gap.in_end - gap.in_start) };
                 read.1[gap.in_start..gap.in_end].copy_from_slice(in_buffer);

From d870f10a2718aa887cd1e3bc2ac4facbabfcfc52 Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Mon, 22 Nov 2021 22:40:58 +0100
Subject: [PATCH 15/24] Updated readme

---
 README.md | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index e918c2f..2e28000 100644
--- a/README.md
+++ b/README.md
@@ -79,7 +79,7 @@ let conn_args = if args.len() > 1 {
     ConnectorArgs::new()
 };
 
-let mut conn = memflow_pcileech::create_connector(&conn_args)
+let mut conn = memflow_pcileech::create_connector(&conn_args, log::Level::Debug)
     .expect("unable to initialize memflow_pcileech");
 ```
 
@@ -110,6 +110,8 @@ On Windows systems the memory map can be obtained from the Registry under the fo
 HKEY_LOCAL_MACHINE\\HARDWARE\\RESOURCEMAP\\System Resources\\Physical Memory\\.Translated
 ```
 
+In case no memory mappings are provided by the user the connector will use the memory mappings found by the os integration (e.g. win32).
+
 ## Troubleshooting
 
 Q: The plugin is not detected/found by memflow

From b403aafb5420a02ca4f919a0e90058e65c46d877 Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Thu, 25 Nov 2021 12:49:05 +0000
Subject: [PATCH 16/24] Fixed an edge case when page boundaries are crossed in
 non-aligned reads which caused the reads to fail silently in leechcore

---
 memflow-pcileech/src/lib.rs | 60 +++++++++++++++++++++++++++++--------
 1 file changed, 47 insertions(+), 13 deletions(-)

diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index e3e17ea..f7dfdad 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -15,7 +15,10 @@ use leechcore_sys::*;
 
 const PAGE_SIZE: usize = 0x1000usize;
 
-const BUF_ALIGN: u64 = 4;
+// the absolute minimum BUF_ALIGN is 4.
+// using 8 bytes as BUF_ALIGN here simplifies things a lot
+// and makes our gap detection code work in cases where page boundaries would be crossed.
+const BUF_ALIGN: u64 = 8;
 const BUF_MIN_LEN: usize = 8;
 const BUF_LEN_ALIGN: usize = 8;
 
@@ -167,8 +170,24 @@ impl PhysicalMemory for PciLeech {
                     unsafe { (*mem).cb = out.len() as u32 };
                 } else {
                     // non-aligned or small read
-                    let mut buffer_len = (out.len() + addr_align as usize).max(BUF_MIN_LEN);
-                    buffer_len += BUF_LEN_ALIGN - (buffer_len & (BUF_LEN_ALIGN - 1));
+                    let page_addr_align = page_addr.to_umem() - addr_align;
+                    let mut buffer_len = out.len() + addr_align as usize;
+                    let buf_align = buffer_len & (BUF_LEN_ALIGN - 1);
+                    if buf_align > 0 {
+                        buffer_len += BUF_LEN_ALIGN - buf_align;
+                    }
+                    buffer_len = buffer_len.max(BUF_MIN_LEN);
+
+                    // note that this always holds true because addr alignment is equal to buf length alignment
+                    assert!(buffer_len >= out.len());
+
+                    // we never want to cross page boundaries, otherwise the read will just not work
+                    assert_eq!(
+                        page_addr.to_umem() - (page_addr.to_umem() & (PAGE_SIZE as umem - 1)),
+                        (page_addr_align + buffer_len as umem - 1)
+                            - ((page_addr_align + buffer_len as umem - 1)
+                                & (PAGE_SIZE as umem - 1))
+                    );
 
                     let buffer = vec![0u8; buffer_len].into_boxed_slice();
                     let buffer_ptr = Box::into_raw(buffer) as *mut u8;
@@ -181,7 +200,7 @@ impl PhysicalMemory for PciLeech {
                         out_end: out.len() + addr_align as usize,
                     });
 
-                    unsafe { (*mem).qwA = page_addr.to_umem() - addr_align };
+                    unsafe { (*mem).qwA = page_addr_align };
                     unsafe { (*mem).__bindgen_anon_1.pb = buffer_ptr };
                     unsafe { (*mem).cb = buffer_len as u32 };
                 }
@@ -272,23 +291,38 @@ impl PhysicalMemory for PciLeech {
                 let len_align = out.len() & (BUF_LEN_ALIGN - 1);
 
                 if addr_align == 0 && len_align == 0 && out.len() >= BUF_MIN_LEN {
-                    // properly aligned read
+                    // properly aligned write
                     unsafe { (*mem).qwA = page_addr.to_umem() };
                     unsafe { (*mem).__bindgen_anon_1.pb = out.as_ptr() as *mut u8 };
                     unsafe { (*mem).cb = out.len() as u32 };
                 } else {
-                    // non-aligned or small read
-                    let mut buffer_len = (out.len() + addr_align as usize).max(BUF_MIN_LEN);
-                    buffer_len += BUF_LEN_ALIGN - (buffer_len & (BUF_LEN_ALIGN - 1));
-
-                    // prepare gap buffer for reading
-                    let write_addr = (page_addr.to_umem() - addr_align).into();
+                    // non-aligned or small write
+                    let page_addr_align = page_addr.to_umem() - addr_align;
+                    let mut buffer_len = out.len() + addr_align as usize;
+                    let buf_align = buffer_len & (BUF_LEN_ALIGN - 1);
+                    if buf_align > 0 {
+                        buffer_len += BUF_LEN_ALIGN - buf_align;
+                    }
+                    buffer_len = buffer_len.max(BUF_MIN_LEN);
+
+                    // note that this always holds true because addr alignment is equal to buf length alignment
+                    assert!(buffer_len >= out.len());
+
+                    // we never want to cross page boundaries, otherwise the write will just not work
+                    assert_eq!(
+                        page_addr.to_umem() - (page_addr.to_umem() & (PAGE_SIZE as umem - 1)),
+                        (page_addr_align + buffer_len as umem - 1)
+                            - ((page_addr_align + buffer_len as umem - 1)
+                                & (PAGE_SIZE as umem - 1))
+                    );
+
+                    // prepare gap buffer for writing
                     let buffer = vec![0u8; buffer_len].into_boxed_slice();
                     let buffer_ptr = Box::into_raw(buffer) as *mut u8;
 
                     // send over to our gaps list
                     gaps.push(WriteGap {
-                        gap_addr: write_addr,
+                        gap_addr: page_addr_align.into(),
                         gap_buffer: buffer_ptr,
                         gap_buffer_len: buffer_len,
                         in_buffer: out.as_ptr(),
@@ -297,7 +331,7 @@ impl PhysicalMemory for PciLeech {
                     });
 
                     // store pointers into pcileech struct for writing (after we dispatched a read)
-                    unsafe { (*mem).qwA = write_addr.to_umem() };
+                    unsafe { (*mem).qwA = page_addr_align };
                     unsafe { (*mem).__bindgen_anon_1.pb = buffer_ptr };
                     unsafe { (*mem).cb = buffer_len as u32 };
                 }

From 9f73d130f954b14b6445d249a1b8c89faeaca9ec Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Mon, 29 Nov 2021 00:05:22 +0100
Subject: [PATCH 17/24] Removed parts of the windows header cbindgen workaround

---
 leechcore-sys/build.rs | 47 ------------------------------------------
 1 file changed, 47 deletions(-)

diff --git a/leechcore-sys/build.rs b/leechcore-sys/build.rs
index dbc6240..dd4ba7f 100644
--- a/leechcore-sys/build.rs
+++ b/leechcore-sys/build.rs
@@ -114,54 +114,7 @@ fn main() {
     // see https://github.com/rust-lang/rust-bindgen/issues/1556
     if target.contains("windows") {
         builder = builder
-            .blacklist_type("LPMONITORINFOEXA?W?")
-            .blacklist_type("LPTOP_LEVEL_EXCEPTION_FILTER")
-            .blacklist_type("MONITORINFOEXA?W?")
-            .blacklist_type("PEXCEPTION_FILTER")
-            .blacklist_type("PEXCEPTION_ROUTINE")
-            .blacklist_type("PSLIST_HEADER")
-            .blacklist_type("PTOP_LEVEL_EXCEPTION_FILTER")
-            .blacklist_type("PVECTORED_EXCEPTION_HANDLER")
-            .blacklist_type("_?L?P?CONTEXT")
-            .blacklist_type("_?L?P?EXCEPTION_POINTERS")
-            .blacklist_type("_?P?DISPATCHER_CONTEXT")
-            .blacklist_type("_?P?EXCEPTION_REGISTRATION_RECORD")
             .blacklist_type("_?P?IMAGE_TLS_DIRECTORY.*")
-            .blacklist_type("_?P?NT_TIB")
-            .blacklist_type("tagMONITORINFOEXA")
-            .blacklist_type("tagMONITORINFOEXW")
-            .blacklist_function("AddVectoredContinueHandler")
-            .blacklist_function("AddVectoredExceptionHandler")
-            .blacklist_function("CopyContext")
-            .blacklist_function("GetThreadContext")
-            .blacklist_function("GetXStateFeaturesMask")
-            .blacklist_function("InitializeContext")
-            .blacklist_function("InitializeContext2")
-            .blacklist_function("InitializeSListHead")
-            .blacklist_function("InterlockedFlushSList")
-            .blacklist_function("InterlockedPopEntrySList")
-            .blacklist_function("InterlockedPushEntrySList")
-            .blacklist_function("InterlockedPushListSListEx")
-            .blacklist_function("LocateXStateFeature")
-            .blacklist_function("QueryDepthSList")
-            .blacklist_function("RaiseFailFastException")
-            .blacklist_function("RtlCaptureContext")
-            .blacklist_function("RtlCaptureContext2")
-            .blacklist_function("RtlFirstEntrySList")
-            .blacklist_function("RtlInitializeSListHead")
-            .blacklist_function("RtlInterlockedFlushSList")
-            .blacklist_function("RtlInterlockedPopEntrySList")
-            .blacklist_function("RtlInterlockedPushEntrySList")
-            .blacklist_function("RtlInterlockedPushListSListEx")
-            .blacklist_function("RtlQueryDepthSList")
-            .blacklist_function("RtlRestoreContext")
-            .blacklist_function("RtlUnwindEx")
-            .blacklist_function("RtlVirtualUnwind")
-            .blacklist_function("SetThreadContext")
-            .blacklist_function("SetUnhandledExceptionFilter")
-            .blacklist_function("SetXStateFeaturesMask")
-            .blacklist_function("UnhandledExceptionFilter")
-            .blacklist_function("__C_specific_handler");
     }
 
     let bindings = builder

From ff7b9929d0807850d8a9f2d5dc392436e3d9b10a Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Mon, 29 Nov 2021 00:07:05 +0100
Subject: [PATCH 18/24] Fixed formatting

---
 leechcore-sys/build.rs | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/leechcore-sys/build.rs b/leechcore-sys/build.rs
index dd4ba7f..4716dde 100644
--- a/leechcore-sys/build.rs
+++ b/leechcore-sys/build.rs
@@ -113,8 +113,7 @@ fn main() {
     // workaround for windows.h
     // see https://github.com/rust-lang/rust-bindgen/issues/1556
     if target.contains("windows") {
-        builder = builder
-            .blacklist_type("_?P?IMAGE_TLS_DIRECTORY.*")
+        builder = builder.blacklist_type("_?P?IMAGE_TLS_DIRECTORY.*")
     }
 
     let bindings = builder

From f0c992abc4f582fde3056e66bd5a2678c5be6d1f Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Tue, 21 Dec 2021 23:26:46 +0100
Subject: [PATCH 19/24] Updated to latest memflow/next

---
 memflow-pcileech/Cargo.toml            |  4 ++--
 memflow-pcileech/examples/ps_win32.rs  |  2 +-
 memflow-pcileech/examples/read_phys.rs |  2 +-
 memflow-pcileech/src/lib.rs            | 11 +++--------
 4 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/memflow-pcileech/Cargo.toml b/memflow-pcileech/Cargo.toml
index 35fde2c..0ca7adf 100644
--- a/memflow-pcileech/Cargo.toml
+++ b/memflow-pcileech/Cargo.toml
@@ -18,12 +18,12 @@ crate-type = ["lib", "cdylib"]
 [dependencies]
 memflow = { git = "https://github.com/memflow/memflow", branch = "next", features = ["plugins", "memmapfiles"] }
 log = { version = "0.4", default-features = false }
-simple_logger = "1.0"
 leechcore-sys = { path = "../leechcore-sys" }
 
 [dev-dependencies]
 clap = "2.33"
-memflow-win32 = { git = "https://github.com/memflow/memflow", branch = "next" }
+simple_logger = "1.0"
+memflow-win32 = { git = "https://github.com/memflow/memflow-win32", branch = "main" }
 
 [features]
 default = []
diff --git a/memflow-pcileech/examples/ps_win32.rs b/memflow-pcileech/examples/ps_win32.rs
index 923030e..6795495 100644
--- a/memflow-pcileech/examples/ps_win32.rs
+++ b/memflow-pcileech/examples/ps_win32.rs
@@ -32,7 +32,7 @@ fn main() {
         Args::new().insert("device", "FPGA")
     };
 
-    let connector = memflow_pcileech::create_connector(&connector_args, Level::Debug)
+    let connector = memflow_pcileech::create_connector(&connector_args)
         .expect("unable to create pcileech connector");
 
     let mut os = Win32Kernel::builder(connector)
diff --git a/memflow-pcileech/examples/read_phys.rs b/memflow-pcileech/examples/read_phys.rs
index 1a09b00..effd309 100644
--- a/memflow-pcileech/examples/read_phys.rs
+++ b/memflow-pcileech/examples/read_phys.rs
@@ -22,7 +22,7 @@ fn main() {
         Args::new().insert("device", "FPGA")
     };
 
-    let mut connector = memflow_pcileech::create_connector(&connector_args, Level::Debug)
+    let mut connector = memflow_pcileech::create_connector(&connector_args)
         .expect("unable to create pcileech connector");
 
     let metadata = connector.metadata();
diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index f7dfdad..760668e 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -5,7 +5,7 @@ use std::ptr;
 use std::slice;
 use std::sync::{Arc, Mutex};
 
-use log::{error, info, Level};
+use log::{error, info};
 
 use memflow::cglue;
 use memflow::mem::phys_mem::*;
@@ -424,14 +424,9 @@ fn validator() -> ArgsValidator {
 
 /// Creates a new PciLeech Connector instance.
 #[connector(name = "pcileech", help_fn = "help", target_list_fn = "target_list")]
-pub fn create_connector(args: &Args, log_level: Level) -> Result<PciLeech> {
-    simple_logger::SimpleLogger::new()
-        .with_level(log_level.to_level_filter())
-        .init()
-        .ok();
-
+pub fn create_connector(args: &Args) -> Result<PciLeech> {
     let validator = validator();
-    match validator.validate(&args) {
+    match validator.validate(args) {
         Ok(_) => {
             let device = args
                 .get("device")

From 2848cd1d0eb415fc45eeb5e8edcc4fdd052fde0d Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Wed, 22 Dec 2021 18:19:05 +0100
Subject: [PATCH 20/24] Updated to latest memflow/next

---
 README.md                   | 1 -
 install.sh                  | 4 ++--
 memflow-pcileech/Cargo.toml | 4 ----
 memflow-pcileech/src/lib.rs | 1 -
 4 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/README.md b/README.md
index 2e28000..054bcde 100644
--- a/README.md
+++ b/README.md
@@ -48,7 +48,6 @@ Remarks: The `install.sh` script does currently not place the `leechcore_ft601_d
 
 ### Building the stand-alone connector for dynamic loading
 
-The stand-alone connector of this library is feature-gated behind the `inventory` feature.
 To compile a dynamic library for use with the connector inventory use the following command:
 
 ```
diff --git a/install.sh b/install.sh
index 82c8cb8..a185e5b 100755
--- a/install.sh
+++ b/install.sh
@@ -8,7 +8,7 @@ if [ ! -z "$1" ] && [ $1 = "--system" ]; then
     if [[ ! -d /usr/lib/memflow ]]; then
         sudo mkdir /usr/lib/memflow
     fi
-    sudo cp target/release/libmemflow_pcileech.so /usr/lib/memflow
+    sudo cp target/release/libmemflow_pcileech.so /usr/lib/memflow/libmemflow_pcileech.7.so
 fi
 
 # install connector in user dir
@@ -16,4 +16,4 @@ echo "installing connector for user in ~/.local/lib/memflow"
 if [[ ! -d ~/.local/lib/memflow ]]; then
     mkdir -p ~/.local/lib/memflow
 fi
-cp target/release/libmemflow_pcileech.so ~/.local/lib/memflow
+cp target/release/libmemflow_pcileech.so ~/.local/lib/memflow/libmemflow_pcileech.7.so
diff --git a/memflow-pcileech/Cargo.toml b/memflow-pcileech/Cargo.toml
index 0ca7adf..b32ad43 100644
--- a/memflow-pcileech/Cargo.toml
+++ b/memflow-pcileech/Cargo.toml
@@ -25,10 +25,6 @@ clap = "2.33"
 simple_logger = "1.0"
 memflow-win32 = { git = "https://github.com/memflow/memflow-win32", branch = "main" }
 
-[features]
-default = []
-inventory = []
-
 [[example]]
 name = "read_phys"
 path = "examples/read_phys.rs"
diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index 760668e..a6cbd37 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -115,7 +115,6 @@ struct WriteGap {
     in_end: usize,
 }
 
-// TODO: handle mem_map
 impl PhysicalMemory for PciLeech {
     fn phys_read_raw_iter<'a>(
         &mut self,

From 9ee8c33fc4b1849ec99fe7abf9710aabc604058f Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Fri, 24 Dec 2021 14:49:08 +0100
Subject: [PATCH 21/24] Updated to latest memflow/next

---
 memflow-pcileech/src/lib.rs | 20 ++++++++------------
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index a6cbd37..9ba851d 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -119,12 +119,11 @@ impl PhysicalMemory for PciLeech {
     fn phys_read_raw_iter<'a>(
         &mut self,
         data: CIterator<PhysicalReadData<'a>>,
-        out_fail: &mut PhysicalReadFailCallback<'_, 'a>,
+        out_fail: &mut ReadFailCallback<'_, 'a>,
     ) -> Result<()> {
         let vec = if let Some(mem_map) = &self.mem_map {
-            let mut callback = &mut |(a, b): (Address, _)| out_fail.call(MemData(a.into(), b));
             mem_map
-                .map_iter(data.map(|MemData(addr, buf)| (addr, buf)), &mut callback)
+                .map_iter(data, out_fail)
                 .map(|d| (d.0 .0.into(), d.1))
                 .collect::<Vec<_>>()
         } else {
@@ -246,12 +245,11 @@ impl PhysicalMemory for PciLeech {
     fn phys_write_raw_iter<'a>(
         &mut self,
         data: CIterator<PhysicalWriteData<'a>>,
-        out_fail: &mut PhysicalWriteFailCallback<'_, 'a>,
+        out_fail: &mut WriteFailCallback<'_, 'a>,
     ) -> Result<()> {
         let vec = if let Some(mem_map) = &self.mem_map {
-            let mut callback = &mut |(a, b): (Address, _)| out_fail.call(MemData(a.into(), b));
             mem_map
-                .map_iter(data.map(|MemData(addr, buf)| (addr, buf)), &mut callback)
+                .map_iter(data, out_fail)
                 .map(|d| (d.0 .0.into(), d.1))
                 .collect::<Vec<_>>()
         } else {
@@ -416,26 +414,24 @@ impl PhysicalMemory for PciLeech {
 
 fn validator() -> ArgsValidator {
     ArgsValidator::new()
-        .arg(ArgDescriptor::new("default").description("the target device to be used by LeechCore"))
         .arg(ArgDescriptor::new("device").description("the target device to be used by LeechCore"))
         .arg(ArgDescriptor::new("memmap").description("the memory map file of the target machine"))
 }
 
 /// Creates a new PciLeech Connector instance.
 #[connector(name = "pcileech", help_fn = "help", target_list_fn = "target_list")]
-pub fn create_connector(args: &Args) -> Result<PciLeech> {
+pub fn create_connector(args: &ConnectorArgs) -> Result<PciLeech> {
     let validator = validator();
-    match validator.validate(args) {
+    match validator.validate(&args.extra_args) {
         Ok(_) => {
-            let device = args
+            let device = args.extra_args
                 .get("device")
-                .or_else(|| args.get_default())
                 .ok_or_else(|| {
                     Error(ErrorOrigin::Connector, ErrorKind::ArgValidation)
                         .log_error("'device' argument is missing")
                 })?;
 
-            if let Some(memmap) = args.get("memmap") {
+            if let Some(memmap) = args.extra_args.get("memmap") {
                 PciLeech::with_mem_map_file(device, memmap)
             } else {
                 PciLeech::new(device)

From 5f50fa57b6c6558ac554e64824524ddd5dfc906c Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Sat, 8 Jan 2022 19:18:09 +0100
Subject: [PATCH 22/24] Updated logging to use simplelog; added basic
 install.rhai script

---
 Cargo.toml                                | 11 +++++----
 install.rhai                              | 27 +++++++++++++++++++++++
 memflow-pcileech/Cargo.toml               |  6 ++---
 memflow-pcileech/examples/ps_inventory.rs | 22 ++++++++++--------
 memflow-pcileech/examples/ps_win32.rs     | 18 +++++++++------
 memflow-pcileech/examples/read_phys.rs    | 18 +++++++++------
 memflow-pcileech/src/lib.rs               | 12 +++++++---
 7 files changed, 81 insertions(+), 33 deletions(-)
 create mode 100644 install.rhai

diff --git a/Cargo.toml b/Cargo.toml
index d543f75..3fdb85f 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -1,3 +1,9 @@
+[profile.bench]
+debug = true
+
+[profile.release]
+lto = "fat"
+
 [workspace]
 members = [
     "leechcore-sys",
@@ -6,7 +12,4 @@ members = [
 default-members = [
     "leechcore-sys",
     "memflow-pcileech",
-]
-
-[profile.release]
-lto = true
+]
\ No newline at end of file
diff --git a/install.rhai b/install.rhai
new file mode 100644
index 0000000..c92e091
--- /dev/null
+++ b/install.rhai
@@ -0,0 +1,27 @@
+
+// builds the connector from a given path (never called by the engine directly)
+fn build_from_path(ctx, repo_path) {
+	info("Installing connector");
+	cargo("build --release --all-features", repo_path);
+	ctx.copy_cargo_plugin_artifact(repo_path, name_to_lib(ctx.crate_name()));
+
+	// TODO: download leechcore_ft601_driver_linux
+}
+
+// builds the connector from local path
+fn build_local(ctx) {
+	build_from_path(ctx, ctx.build_path())
+}
+
+fn get_source(ctx) {
+	ctx.clone_repository()
+}
+
+// builds the connector from source
+fn build_from_source(ctx) {
+	build_from_path(ctx, get_source(ctx))
+}
+
+// downloads a binary release of the plugin, still needs dkms
+fn install(ctx) {
+}
diff --git a/memflow-pcileech/Cargo.toml b/memflow-pcileech/Cargo.toml
index b32ad43..2e9f530 100644
--- a/memflow-pcileech/Cargo.toml
+++ b/memflow-pcileech/Cargo.toml
@@ -17,12 +17,12 @@ crate-type = ["lib", "cdylib"]
 
 [dependencies]
 memflow = { git = "https://github.com/memflow/memflow", branch = "next", features = ["plugins", "memmapfiles"] }
-log = { version = "0.4", default-features = false }
 leechcore-sys = { path = "../leechcore-sys" }
+log = "^0.4.14"
 
 [dev-dependencies]
-clap = "2.33"
-simple_logger = "1.0"
+clap = { version = "^3.0.5", features = ["cargo"] }
+simplelog = "^0.11.1"
 memflow-win32 = { git = "https://github.com/memflow/memflow-win32", branch = "main" }
 
 [[example]]
diff --git a/memflow-pcileech/examples/ps_inventory.rs b/memflow-pcileech/examples/ps_inventory.rs
index 1ccfd9f..1ef0996 100644
--- a/memflow-pcileech/examples/ps_inventory.rs
+++ b/memflow-pcileech/examples/ps_inventory.rs
@@ -22,23 +22,27 @@ use log::{info, Level};
 use memflow::prelude::v1::*;
 
 fn main() {
-    simple_logger::SimpleLogger::new()
-        .with_level(Level::Debug.to_level_filter())
-        .init()
-        .unwrap();
+    simplelog::TermLogger::init(
+        Level::Debug.to_level_filter(),
+        simplelog::Config::default(),
+        simplelog::TerminalMode::Stdout,
+        simplelog::ColorChoice::Auto,
+    )
+    .unwrap();
 
     let connector_args = if let Some(arg) = args().nth(1) {
-        Args::parse(arg.as_ref()).expect("unable to parse command line arguments")
+        arg.parse()
     } else {
-        Args::new().insert("device", "FPGA")
-    };
+        "device=FPGA".parse()
+    }
+    .expect("unable to parse command line arguments");
 
     let inventory = Inventory::scan();
     let connector = inventory
-        .create_connector("pcileech", None, &connector_args)
+        .create_connector("pcileech", None, Some(&connector_args))
         .expect("unable to create pcileech connector");
     let mut os = inventory
-        .create_os("win32", Some(connector), &Args::default())
+        .create_os("win32", Some(connector), None)
         .expect("unable to create win32 instance with pcileech connector");
 
     let process_list = os.process_info_list().expect("unable to read process list");
diff --git a/memflow-pcileech/examples/ps_win32.rs b/memflow-pcileech/examples/ps_win32.rs
index 6795495..1e28331 100644
--- a/memflow-pcileech/examples/ps_win32.rs
+++ b/memflow-pcileech/examples/ps_win32.rs
@@ -21,16 +21,20 @@ use memflow::prelude::v1::*;
 use memflow_win32::prelude::v1::*;
 
 fn main() {
-    simple_logger::SimpleLogger::new()
-        .with_level(Level::Debug.to_level_filter())
-        .init()
-        .unwrap();
+    simplelog::TermLogger::init(
+        Level::Debug.to_level_filter(),
+        simplelog::Config::default(),
+        simplelog::TerminalMode::Stdout,
+        simplelog::ColorChoice::Auto,
+    )
+    .unwrap();
 
     let connector_args = if let Some(arg) = args().nth(1) {
-        Args::parse(arg.as_ref()).expect("unable to parse command line arguments")
+        arg.parse()
     } else {
-        Args::new().insert("device", "FPGA")
-    };
+        "device=FPGA".parse()
+    }
+    .expect("unable to parse command line arguments");
 
     let connector = memflow_pcileech::create_connector(&connector_args)
         .expect("unable to create pcileech connector");
diff --git a/memflow-pcileech/examples/read_phys.rs b/memflow-pcileech/examples/read_phys.rs
index effd309..7d5d572 100644
--- a/memflow-pcileech/examples/read_phys.rs
+++ b/memflow-pcileech/examples/read_phys.rs
@@ -11,16 +11,20 @@ use log::{info, Level};
 use memflow::prelude::v1::*;
 
 fn main() {
-    simple_logger::SimpleLogger::new()
-        .with_level(Level::Debug.to_level_filter())
-        .init()
-        .unwrap();
+    simplelog::TermLogger::init(
+        Level::Debug.to_level_filter(),
+        simplelog::Config::default(),
+        simplelog::TerminalMode::Stdout,
+        simplelog::ColorChoice::Auto,
+    )
+    .unwrap();
 
     let connector_args = if let Some(arg) = args().nth(1) {
-        Args::parse(arg.as_ref()).expect("unable to parse command line arguments")
+        arg.parse()
     } else {
-        Args::new().insert("device", "FPGA")
-    };
+        "device=FPGA".parse()
+    }
+    .expect("unable to parse command line arguments");
 
     let mut connector = memflow_pcileech::create_connector(&connector_args)
         .expect("unable to create pcileech connector");
diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index 9ba851d..56c7533 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -414,6 +414,7 @@ impl PhysicalMemory for PciLeech {
 
 fn validator() -> ArgsValidator {
     ArgsValidator::new()
+        .arg(ArgDescriptor::new("default").description("the target device to be used by LeechCore"))
         .arg(ArgDescriptor::new("device").description("the target device to be used by LeechCore"))
         .arg(ArgDescriptor::new("memmap").description("the memory map file of the target machine"))
 }
@@ -422,16 +423,20 @@ fn validator() -> ArgsValidator {
 #[connector(name = "pcileech", help_fn = "help", target_list_fn = "target_list")]
 pub fn create_connector(args: &ConnectorArgs) -> Result<PciLeech> {
     let validator = validator();
-    match validator.validate(&args.extra_args) {
+
+    let args = &args.extra_args;
+
+    match validator.validate(args) {
         Ok(_) => {
-            let device = args.extra_args
+            let device = args
                 .get("device")
+                .or_else(|| args.get_default())
                 .ok_or_else(|| {
                     Error(ErrorOrigin::Connector, ErrorKind::ArgValidation)
                         .log_error("'device' argument is missing")
                 })?;
 
-            if let Some(memmap) = args.extra_args.get("memmap") {
+            if let Some(memmap) = args.get("memmap") {
                 PciLeech::with_mem_map_file(device, memmap)
             } else {
                 PciLeech::new(device)
@@ -466,5 +471,6 @@ Available arguments are:
 
 /// Retrieve a list of all currently available PciLeech targets.
 pub fn target_list() -> Result<Vec<TargetInfo>> {
+    // TODO: check if usb is connected, then list 1 target
     Ok(vec![])
 }

From f03880bbc7812f6ffee4bf66adb0d9ce13332f38 Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Sat, 8 Jan 2022 21:29:37 +0100
Subject: [PATCH 23/24] Added cargo.lock file to enable reproducible builds

---
 .gitignore |    1 -
 Cargo.lock | 1547 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 1547 insertions(+), 1 deletion(-)
 create mode 100644 Cargo.lock

diff --git a/.gitignore b/.gitignore
index 3582899..054b65f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -2,4 +2,3 @@
 **/*.rs.bk
 *.swp
 .vscode
-Cargo.lock
diff --git a/Cargo.lock b/Cargo.lock
new file mode 100644
index 0000000..cd15928
--- /dev/null
+++ b/Cargo.lock
@@ -0,0 +1,1547 @@
+# This file is automatically @generated by Cargo.
+# It is not intended for manual editing.
+version = 3
+
+[[package]]
+name = "abi_stable"
+version = "0.10.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3c8f0d5c8e09e8b591f6db9f56b006c9b9e7a44064acb274411ae51aaaa1364d"
+dependencies = [
+ "abi_stable_derive",
+ "abi_stable_shared",
+ "core_extensions",
+ "crossbeam-channel",
+ "generational-arena",
+ "libloading",
+ "lock_api",
+ "parking_lot",
+ "paste",
+ "repr_offset",
+ "rustc_version 0.4.0",
+ "serde",
+ "serde_derive",
+ "serde_json",
+]
+
+[[package]]
+name = "abi_stable_derive"
+version = "0.10.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3b9810ef8debee5544010d92dac0b88b32853cd5bd5ca3298243c99e931da0f0"
+dependencies = [
+ "abi_stable_shared",
+ "as_derive_utils",
+ "core_extensions",
+ "proc-macro2",
+ "quote",
+ "rustc_version 0.2.3",
+ "syn",
+ "typed-arena",
+]
+
+[[package]]
+name = "abi_stable_shared"
+version = "0.10.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ece9da89066e018d908b48755e17cdd08a46ce222f84b1f226e837f836f84a5f"
+dependencies = [
+ "core_extensions",
+]
+
+[[package]]
+name = "adler"
+version = "1.0.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f26201604c87b1e01bd3d98f8d5d9a8fcbb815e8cedb41ffccbeb4bf593a35fe"
+
+[[package]]
+name = "ahash"
+version = "0.7.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "fcb51a0695d8f838b1ee009b3fbf66bda078cd64590202a864a8f3e8c4315c47"
+dependencies = [
+ "getrandom",
+ "once_cell",
+ "version_check",
+]
+
+[[package]]
+name = "aho-corasick"
+version = "0.7.18"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1e37cfd5e7657ada45f742d6e99ca5788580b5c529dc78faf11ece6dc702656f"
+dependencies = [
+ "memchr",
+]
+
+[[package]]
+name = "ansi_term"
+version = "0.12.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d52a9bb7ec0cf484c551830a7ce27bd20d67eac647e1befb56b0be4ee39a55d2"
+dependencies = [
+ "winapi",
+]
+
+[[package]]
+name = "as_derive_utils"
+version = "0.10.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e0a26fa495cefb8c86d9ce183b3f39ad11678e54fb3c20e6b7dbd87770811d9b"
+dependencies = [
+ "core_extensions",
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "atty"
+version = "0.2.14"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d9b39be18770d11421cdb1b9947a45dd3f37e93092cbf377614828a319d5fee8"
+dependencies = [
+ "hermit-abi",
+ "libc",
+ "winapi",
+]
+
+[[package]]
+name = "autocfg"
+version = "1.0.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "cdb031dd78e28731d87d56cc8ffef4a8f36ca26c38fe2de700543e627f8a464a"
+
+[[package]]
+name = "base64"
+version = "0.13.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "904dfeac50f3cdaba28fc6f57fdcddb75f49ed61346676a78c4ffe55877802fd"
+
+[[package]]
+name = "bindgen"
+version = "0.56.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2da379dbebc0b76ef63ca68d8fc6e71c0f13e59432e0987e508c1820e6ab5239"
+dependencies = [
+ "bitflags",
+ "cexpr",
+ "clang-sys",
+ "clap 2.34.0",
+ "env_logger",
+ "lazy_static",
+ "lazycell",
+ "log",
+ "peeking_take_while",
+ "proc-macro2",
+ "quote",
+ "regex",
+ "rustc-hash",
+ "shlex",
+ "which",
+]
+
+[[package]]
+name = "bit_field"
+version = "0.10.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "dcb6dd1c2376d2e096796e234a70e17e94cc2d5d54ff8ce42b28cef1d0d359a4"
+
+[[package]]
+name = "bitflags"
+version = "1.3.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a"
+
+[[package]]
+name = "bumpalo"
+version = "3.9.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a4a45a46ab1f2412e53d3a0ade76ffad2025804294569aae387231a0cd6e0899"
+
+[[package]]
+name = "cc"
+version = "1.0.72"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "22a9137b95ea06864e018375b72adfb7db6e6f68cfc8df5a04d00288050485ee"
+
+[[package]]
+name = "cexpr"
+version = "0.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f4aedb84272dbe89af497cf81375129abda4fc0a9e7c5d317498c15cc30c0d27"
+dependencies = [
+ "nom",
+]
+
+[[package]]
+name = "cfg-if"
+version = "0.1.10"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "4785bdd1c96b2a846b2bd7cc02e86b6b3dbf14e7e53446c4f54c92a361040822"
+
+[[package]]
+name = "cfg-if"
+version = "1.0.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
+
+[[package]]
+name = "cglue"
+version = "0.2.5"
+source = "git+https://github.com/h33p/cglue.git?branch=main#02e0f1089fe942edcda0391d12a008b6459bcc99"
+dependencies = [
+ "abi_stable",
+ "cglue-macro",
+ "no-std-compat",
+ "serde",
+]
+
+[[package]]
+name = "cglue-gen"
+version = "0.2.2"
+source = "git+https://github.com/h33p/cglue.git?branch=main#02e0f1089fe942edcda0391d12a008b6459bcc99"
+dependencies = [
+ "itertools",
+ "lazy_static",
+ "proc-macro-crate",
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "cglue-macro"
+version = "0.2.1"
+source = "git+https://github.com/h33p/cglue.git?branch=main#02e0f1089fe942edcda0391d12a008b6459bcc99"
+dependencies = [
+ "cglue-gen",
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "chrono"
+version = "0.4.19"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "670ad68c9088c2a963aaa298cb369688cf3f9465ce5e2d4ca10e6e0098a1ce73"
+dependencies = [
+ "libc",
+ "num-integer",
+ "num-traits",
+ "time",
+ "winapi",
+]
+
+[[package]]
+name = "chunked_transfer"
+version = "1.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "fff857943da45f546682664a79488be82e69e43c1a7a2307679ab9afb3a66d2e"
+
+[[package]]
+name = "clang-sys"
+version = "1.3.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "fa66045b9cb23c2e9c1520732030608b02ee07e5cfaa5a521ec15ded7fa24c90"
+dependencies = [
+ "glob",
+ "libc",
+ "libloading",
+]
+
+[[package]]
+name = "clap"
+version = "2.34.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a0610544180c38b88101fecf2dd634b174a62eef6946f84dfc6a7127512b381c"
+dependencies = [
+ "ansi_term",
+ "atty",
+ "bitflags",
+ "strsim 0.8.0",
+ "textwrap 0.11.0",
+ "unicode-width",
+ "vec_map",
+]
+
+[[package]]
+name = "clap"
+version = "3.0.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f6f34b09b9ee8c7c7b400fe2f8df39cafc9538b03d6ba7f4ae13e4cb90bfbb7d"
+dependencies = [
+ "atty",
+ "bitflags",
+ "indexmap",
+ "lazy_static",
+ "os_str_bytes",
+ "strsim 0.10.0",
+ "termcolor",
+ "textwrap 0.14.2",
+]
+
+[[package]]
+name = "coarsetime"
+version = "0.1.20"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5b6ec6f6e80e839eb22bd61b18f19a8f2ae3f8bda9cf0fdce9dd96c9c5df8393"
+dependencies = [
+ "libc",
+ "once_cell",
+ "wasi",
+ "wasm-bindgen",
+]
+
+[[package]]
+name = "console"
+version = "0.15.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a28b32d32ca44b70c3e4acd7db1babf555fa026e385fb95f18028f88848b3c31"
+dependencies = [
+ "encode_unicode",
+ "libc",
+ "once_cell",
+ "terminal_size",
+ "winapi",
+]
+
+[[package]]
+name = "core_extensions"
+version = "1.5.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "79b110b7cd430bd590fa60a5ba58a383488dab61912318bfb05d968a80cdda6d"
+dependencies = [
+ "core_extensions_proc_macros",
+]
+
+[[package]]
+name = "core_extensions_proc_macros"
+version = "1.5.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c348a81513f573054124b9f10e258a654a0519b65f2dba0142307bd3c7b5b8b6"
+
+[[package]]
+name = "crc32fast"
+version = "1.3.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "738c290dfaea84fc1ca15ad9c168d083b05a714e1efddd8edaab678dc28d2836"
+dependencies = [
+ "cfg-if 1.0.0",
+]
+
+[[package]]
+name = "crossbeam-channel"
+version = "0.5.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e54ea8bc3fb1ee042f5aace6e3c6e025d3874866da222930f70ce62aceba0bfa"
+dependencies = [
+ "cfg-if 1.0.0",
+ "crossbeam-utils",
+]
+
+[[package]]
+name = "crossbeam-utils"
+version = "0.8.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "cfcae03edb34f947e64acdb1c33ec169824e20657e9ecb61cef6c8c74dcb8120"
+dependencies = [
+ "cfg-if 1.0.0",
+ "lazy_static",
+]
+
+[[package]]
+name = "ctor"
+version = "0.1.21"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ccc0a48a9b826acdf4028595adc9db92caea352f7af011a3034acd172a52a0aa"
+dependencies = [
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "darling"
+version = "0.13.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d0d720b8683f8dd83c65155f0530560cba68cd2bf395f6513a483caee57ff7f4"
+dependencies = [
+ "darling_core",
+ "darling_macro",
+]
+
+[[package]]
+name = "darling_core"
+version = "0.13.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7a340f241d2ceed1deb47ae36c4144b2707ec7dd0b649f894cb39bb595986324"
+dependencies = [
+ "fnv",
+ "ident_case",
+ "proc-macro2",
+ "quote",
+ "strsim 0.10.0",
+ "syn",
+]
+
+[[package]]
+name = "darling_macro"
+version = "0.13.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "72c41b3b7352feb3211a0d743dc5700a4e3b60f51bd2b368892d1e0f9a95f44b"
+dependencies = [
+ "darling_core",
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "dataview"
+version = "0.1.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "47a802a2cad0ff4dfc4f3110da174b7a6928c315cae523e88638cfb72941b4d5"
+
+[[package]]
+name = "dirs"
+version = "4.0.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ca3aa72a6f96ea37bbc5aa912f6788242832f75369bdfdadcb0e38423f100059"
+dependencies = [
+ "dirs-sys",
+]
+
+[[package]]
+name = "dirs-sys"
+version = "0.3.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "03d86534ed367a67548dc68113a0f5db55432fdfbb6e6f9d77704397d95d5780"
+dependencies = [
+ "libc",
+ "redox_users",
+ "winapi",
+]
+
+[[package]]
+name = "either"
+version = "1.6.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e78d4f1cc4ae33bbfc157ed5d5a5ef3bc29227303d595861deb238fcec4e9457"
+
+[[package]]
+name = "encode_unicode"
+version = "0.3.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a357d28ed41a50f9c765dbfe56cbc04a64e53e5fc58ba79fbc34c10ef3df831f"
+
+[[package]]
+name = "env_logger"
+version = "0.8.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a19187fea3ac7e84da7dacf48de0c45d63c6a76f9490dae389aead16c243fce3"
+dependencies = [
+ "atty",
+ "humantime",
+ "log",
+ "regex",
+ "termcolor",
+]
+
+[[package]]
+name = "fallible-iterator"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "4443176a9f2c162692bd3d352d745ef9413eec5782a80d8fd6f8a1ac692a07f7"
+
+[[package]]
+name = "fixed-slice-vec"
+version = "0.8.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "fafbcddfce402d6170ee6e5037f032dd96233ce73c66f7d83a4150fb76814b44"
+
+[[package]]
+name = "flate2"
+version = "1.0.22"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1e6988e897c1c9c485f43b47a529cef42fde0547f9d8d41a7062518f1d8fc53f"
+dependencies = [
+ "cfg-if 1.0.0",
+ "crc32fast",
+ "libc",
+ "miniz_oxide",
+]
+
+[[package]]
+name = "fnv"
+version = "1.0.7"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3f9eec918d3f24069decb9af1554cad7c880e2da24a9afd88aca000531ab82c1"
+
+[[package]]
+name = "form_urlencoded"
+version = "1.0.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5fc25a87fa4fd2094bffb06925852034d90a17f0d1e05197d4956d3555752191"
+dependencies = [
+ "matches",
+ "percent-encoding",
+]
+
+[[package]]
+name = "generational-arena"
+version = "0.2.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8e1d3b771574f62d0548cee0ad9057857e9fc25d7a3335f140c84f6acd0bf601"
+dependencies = [
+ "cfg-if 0.1.10",
+]
+
+[[package]]
+name = "getrandom"
+version = "0.2.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7fcd999463524c52659517fe2cea98493cfe485d10565e7b0fb07dbba7ad2753"
+dependencies = [
+ "cfg-if 1.0.0",
+ "libc",
+ "wasi",
+]
+
+[[package]]
+name = "glob"
+version = "0.3.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9b919933a397b79c37e33b77bb2aa3dc8eb6e165ad809e58ff75bc7db2e34574"
+
+[[package]]
+name = "goblin"
+version = "0.4.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "32401e89c6446dcd28185931a01b1093726d0356820ac744023e6850689bf926"
+dependencies = [
+ "log",
+ "plain",
+ "scroll",
+]
+
+[[package]]
+name = "hashbrown"
+version = "0.11.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ab5ef0d4909ef3724cc8cce6ccc8572c5c817592e9285f5464f8e86f8bd3726e"
+dependencies = [
+ "ahash",
+]
+
+[[package]]
+name = "hermit-abi"
+version = "0.1.19"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "62b467343b94ba476dcb2500d242dadbb39557df889310ac77c5d99100aaac33"
+dependencies = [
+ "libc",
+]
+
+[[package]]
+name = "humantime"
+version = "2.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9a3a5bfb195931eeb336b2a7b4d761daec841b97f947d34394601737a7bba5e4"
+
+[[package]]
+name = "ident_case"
+version = "1.0.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b9e0384b61958566e926dc50660321d12159025e767c18e043daf26b70104c39"
+
+[[package]]
+name = "idna"
+version = "0.2.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "418a0a6fab821475f634efe3ccc45c013f742efe03d853e8d3355d5cb850ecf8"
+dependencies = [
+ "matches",
+ "unicode-bidi",
+ "unicode-normalization",
+]
+
+[[package]]
+name = "indexmap"
+version = "1.8.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "282a6247722caba404c065016bbfa522806e51714c34f5dfc3e4a3a46fcb4223"
+dependencies = [
+ "autocfg",
+ "hashbrown",
+]
+
+[[package]]
+name = "indicatif"
+version = "0.16.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2d207dc617c7a380ab07ff572a6e52fa202a2a8f355860ac9c38e23f8196be1b"
+dependencies = [
+ "console",
+ "lazy_static",
+ "number_prefix",
+ "regex",
+]
+
+[[package]]
+name = "instant"
+version = "0.1.12"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7a5bbe824c507c5da5956355e86a746d82e0e1464f65d862cc5e71da70e94b2c"
+dependencies = [
+ "cfg-if 1.0.0",
+]
+
+[[package]]
+name = "itertools"
+version = "0.10.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a9a9d19fa1e79b6215ff29b9d6880b706147f16e9b1dbb1e4e5947b5b02bc5e3"
+dependencies = [
+ "either",
+]
+
+[[package]]
+name = "itoa"
+version = "1.0.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1aab8fc367588b89dcee83ab0fd66b72b50b72fa1904d7095045ace2b0c81c35"
+
+[[package]]
+name = "js-sys"
+version = "0.3.55"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7cc9ffccd38c451a86bf13657df244e9c3f37493cce8e5e21e940963777acc84"
+dependencies = [
+ "wasm-bindgen",
+]
+
+[[package]]
+name = "lazy_static"
+version = "1.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e2abad23fbc42b3700f2f279844dc832adb2b2eb069b2df918f455c4e18cc646"
+
+[[package]]
+name = "lazycell"
+version = "1.3.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "830d08ce1d1d941e6b30645f1a0eb5643013d835ce3779a5fc208261dbe10f55"
+
+[[package]]
+name = "leechcore-sys"
+version = "0.1.5"
+dependencies = [
+ "bindgen",
+ "cc",
+ "ctor",
+ "pkg-config",
+]
+
+[[package]]
+name = "libc"
+version = "0.2.112"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1b03d17f364a3a042d5e5d46b053bbbf82c92c9430c592dd4c064dc6ee997125"
+
+[[package]]
+name = "libloading"
+version = "0.7.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "afe203d669ec979b7128619bae5a63b7b42e9203c1b29146079ee05e2f604b52"
+dependencies = [
+ "cfg-if 1.0.0",
+ "winapi",
+]
+
+[[package]]
+name = "lock_api"
+version = "0.4.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "712a4d093c9976e24e7dbca41db895dabcbac38eb5f4045393d17a95bdfb1109"
+dependencies = [
+ "scopeguard",
+]
+
+[[package]]
+name = "log"
+version = "0.4.14"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "51b9bbe6c47d51fc3e1a9b945965946b4c44142ab8792c50835a980d362c2710"
+dependencies = [
+ "cfg-if 1.0.0",
+]
+
+[[package]]
+name = "matches"
+version = "0.1.9"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a3e378b66a060d48947b590737b30a1be76706c8dd7b8ba0f2fe3989c68a853f"
+
+[[package]]
+name = "memchr"
+version = "2.4.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "308cc39be01b73d0d18f82a0e7b2a3df85245f84af96fdddc5d202d27e47b86a"
+
+[[package]]
+name = "memflow"
+version = "0.1.5"
+source = "git+https://github.com/memflow/memflow?branch=next#8627a9d575206461bec2b9c236a80af4879259e3"
+dependencies = [
+ "abi_stable",
+ "bitflags",
+ "bumpalo",
+ "cglue",
+ "coarsetime",
+ "dataview",
+ "dirs",
+ "fixed-slice-vec",
+ "goblin",
+ "hashbrown",
+ "itertools",
+ "libloading",
+ "log",
+ "memflow-derive",
+ "memmap",
+ "no-std-compat",
+ "once_cell",
+ "rangemap",
+ "serde",
+ "smallvec",
+ "toml",
+ "x86_64",
+]
+
+[[package]]
+name = "memflow-derive"
+version = "0.1.5"
+source = "git+https://github.com/memflow/memflow?branch=next#8627a9d575206461bec2b9c236a80af4879259e3"
+dependencies = [
+ "darling",
+ "proc-macro-crate",
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "memflow-pcileech"
+version = "0.1.5"
+dependencies = [
+ "clap 3.0.5",
+ "leechcore-sys",
+ "log",
+ "memflow",
+ "memflow-win32",
+ "simplelog",
+]
+
+[[package]]
+name = "memflow-win32"
+version = "0.1.5"
+source = "git+https://github.com/memflow/memflow-win32?branch=main#e94c7120296b0fc0404fe79b41f87f646362c28e"
+dependencies = [
+ "dirs",
+ "goblin",
+ "indicatif",
+ "log",
+ "memflow",
+ "no-std-compat",
+ "pdb",
+ "pelite",
+ "progress-streams",
+ "regex",
+ "serde",
+ "toml",
+ "ureq",
+ "widestring",
+]
+
+[[package]]
+name = "memmap"
+version = "0.7.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6585fd95e7bb50d6cc31e20d4cf9afb4e2ba16c5846fc76793f11218da9c475b"
+dependencies = [
+ "libc",
+ "winapi",
+]
+
+[[package]]
+name = "miniz_oxide"
+version = "0.4.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a92518e98c078586bc6c934028adcca4c92a53d6a958196de835170a01d84e4b"
+dependencies = [
+ "adler",
+ "autocfg",
+]
+
+[[package]]
+name = "no-std-compat"
+version = "0.4.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b93853da6d84c2e3c7d730d6473e8817692dd89be387eb01b94d7f108ecb5b8c"
+
+[[package]]
+name = "nom"
+version = "5.1.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ffb4262d26ed83a1c0a33a38fe2bb15797329c85770da05e6b828ddb782627af"
+dependencies = [
+ "memchr",
+ "version_check",
+]
+
+[[package]]
+name = "num-integer"
+version = "0.1.44"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d2cc698a63b549a70bc047073d2949cce27cd1c7b0a4a862d08a8031bc2801db"
+dependencies = [
+ "autocfg",
+ "num-traits",
+]
+
+[[package]]
+name = "num-traits"
+version = "0.2.14"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9a64b1ec5cda2586e284722486d802acf1f7dbdc623e2bfc57e65ca1cd099290"
+dependencies = [
+ "autocfg",
+]
+
+[[package]]
+name = "number_prefix"
+version = "0.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "830b246a0e5f20af87141b25c173cd1b609bd7779a4617d6ec582abaf90870f3"
+
+[[package]]
+name = "once_cell"
+version = "1.9.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "da32515d9f6e6e489d7bc9d84c71b060db7247dc035bbe44eac88cf87486d8d5"
+
+[[package]]
+name = "os_str_bytes"
+version = "6.0.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8e22443d1643a904602595ba1cd8f7d896afe56d26712531c5ff73a15b2fbf64"
+dependencies = [
+ "memchr",
+]
+
+[[package]]
+name = "parking_lot"
+version = "0.11.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7d17b78036a60663b797adeaee46f5c9dfebb86948d1255007a1d6be0271ff99"
+dependencies = [
+ "instant",
+ "lock_api",
+ "parking_lot_core",
+]
+
+[[package]]
+name = "parking_lot_core"
+version = "0.8.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d76e8e1493bcac0d2766c42737f34458f1c8c50c0d23bcb24ea953affb273216"
+dependencies = [
+ "cfg-if 1.0.0",
+ "instant",
+ "libc",
+ "redox_syscall",
+ "smallvec",
+ "winapi",
+]
+
+[[package]]
+name = "paste"
+version = "1.0.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0744126afe1a6dd7f394cb50a716dbe086cb06e255e53d8d0185d82828358fb5"
+
+[[package]]
+name = "pdb"
+version = "0.7.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "13f4d162ecaaa1467de5afbe62d597757b674b51da8bb4e587430c5fdb2af7aa"
+dependencies = [
+ "fallible-iterator",
+ "scroll",
+ "uuid",
+]
+
+[[package]]
+name = "peeking_take_while"
+version = "0.1.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "19b17cddbe7ec3f8bc800887bab5e717348c95ea2ca0b1bf0837fb964dc67099"
+
+[[package]]
+name = "pelite"
+version = "0.9.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8c270b1a0c279bbcb4cff3d2294121731c48ee68f0435d26cf71018a853cb890"
+dependencies = [
+ "dataview",
+ "no-std-compat",
+ "pelite-macros",
+ "serde",
+]
+
+[[package]]
+name = "pelite-macros"
+version = "0.1.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7a7cf3f8ecebb0f4895f4892a8be0a0dc81b498f9d56735cb769dc31bf00815b"
+
+[[package]]
+name = "percent-encoding"
+version = "2.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d4fd5641d01c8f18a23da7b6fe29298ff4b55afcccdf78973b24cf3175fee32e"
+
+[[package]]
+name = "pkg-config"
+version = "0.3.24"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "58893f751c9b0412871a09abd62ecd2a00298c6c83befa223ef98c52aef40cbe"
+
+[[package]]
+name = "plain"
+version = "0.2.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b4596b6d070b27117e987119b4dac604f3c58cfb0b191112e24771b2faeac1a6"
+
+[[package]]
+name = "proc-macro-crate"
+version = "1.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1ebace6889caf889b4d3f76becee12e90353f2b8c7d875534a71e5742f8f6f83"
+dependencies = [
+ "thiserror",
+ "toml",
+]
+
+[[package]]
+name = "proc-macro2"
+version = "1.0.36"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c7342d5883fbccae1cc37a2353b09c87c9b0f3afd73f5fb9bba687a1f733b029"
+dependencies = [
+ "unicode-xid",
+]
+
+[[package]]
+name = "progress-streams"
+version = "1.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e965d96c8162c607b0cd8d66047ad3c9fd35273c134d994327882c6e47f986a7"
+
+[[package]]
+name = "quote"
+version = "1.0.14"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "47aa80447ce4daf1717500037052af176af5d38cc3e571d9ec1c7353fc10c87d"
+dependencies = [
+ "proc-macro2",
+]
+
+[[package]]
+name = "rangemap"
+version = "0.1.14"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3929836cb64d09ee7deee59635c3d9bffbc1c0373e247efff6272abd62a11baa"
+
+[[package]]
+name = "redox_syscall"
+version = "0.2.10"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8383f39639269cde97d255a32bdb68c047337295414940c68bdd30c2e13203ff"
+dependencies = [
+ "bitflags",
+]
+
+[[package]]
+name = "redox_users"
+version = "0.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "528532f3d801c87aec9def2add9ca802fe569e44a544afe633765267840abe64"
+dependencies = [
+ "getrandom",
+ "redox_syscall",
+]
+
+[[package]]
+name = "regex"
+version = "1.5.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d07a8629359eb56f1e2fb1652bb04212c072a87ba68546a04065d525673ac461"
+dependencies = [
+ "aho-corasick",
+ "memchr",
+ "regex-syntax",
+]
+
+[[package]]
+name = "regex-syntax"
+version = "0.6.25"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f497285884f3fcff424ffc933e56d7cbca511def0c9831a7f9b5f6153e3cc89b"
+
+[[package]]
+name = "repr_offset"
+version = "0.2.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "663e92f38214b9e51fa305902788f5fb45fb60027b727556618fc53ba1946112"
+dependencies = [
+ "tstr",
+]
+
+[[package]]
+name = "ring"
+version = "0.16.20"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3053cf52e236a3ed746dfc745aa9cacf1b791d846bdaf412f60a8d7d6e17c8fc"
+dependencies = [
+ "cc",
+ "libc",
+ "once_cell",
+ "spin",
+ "untrusted",
+ "web-sys",
+ "winapi",
+]
+
+[[package]]
+name = "rustc-hash"
+version = "1.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "08d43f7aa6b08d49f382cde6a7982047c3426db949b1424bc4b7ec9ae12c6ce2"
+
+[[package]]
+name = "rustc_version"
+version = "0.2.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "138e3e0acb6c9fb258b19b67cb8abd63c00679d2851805ea151465464fe9030a"
+dependencies = [
+ "semver 0.9.0",
+]
+
+[[package]]
+name = "rustc_version"
+version = "0.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "bfa0f585226d2e68097d4f95d113b15b83a82e819ab25717ec0590d9584ef366"
+dependencies = [
+ "semver 1.0.4",
+]
+
+[[package]]
+name = "rustls"
+version = "0.20.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d37e5e2290f3e040b594b1a9e04377c2c671f1a1cfd9bfdef82106ac1c113f84"
+dependencies = [
+ "log",
+ "ring",
+ "sct",
+ "webpki",
+]
+
+[[package]]
+name = "ryu"
+version = "1.0.9"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "73b4b750c782965c211b42f022f59af1fbceabdd026623714f104152f1ec149f"
+
+[[package]]
+name = "scopeguard"
+version = "1.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d29ab0c6d3fc0ee92fe66e2d99f700eab17a8d57d1c1d3b748380fb20baa78cd"
+
+[[package]]
+name = "scroll"
+version = "0.10.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "fda28d4b4830b807a8b43f7b0e6b5df875311b3e7621d84577188c175b6ec1ec"
+dependencies = [
+ "scroll_derive",
+]
+
+[[package]]
+name = "scroll_derive"
+version = "0.10.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "aaaae8f38bb311444cfb7f1979af0bc9240d95795f75f9ceddf6a59b79ceffa0"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "sct"
+version = "0.7.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d53dcdb7c9f8158937a7981b48accfd39a43af418591a5d008c7b22b5e1b7ca4"
+dependencies = [
+ "ring",
+ "untrusted",
+]
+
+[[package]]
+name = "semver"
+version = "0.9.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1d7eb9ef2c18661902cc47e535f9bc51b78acd254da71d375c2f6720d9a40403"
+dependencies = [
+ "semver-parser",
+]
+
+[[package]]
+name = "semver"
+version = "1.0.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "568a8e6258aa33c13358f81fd834adb854c6f7c9468520910a9b1e8fac068012"
+
+[[package]]
+name = "semver-parser"
+version = "0.7.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3"
+
+[[package]]
+name = "serde"
+version = "1.0.133"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "97565067517b60e2d1ea8b268e59ce036de907ac523ad83a0475da04e818989a"
+dependencies = [
+ "serde_derive",
+]
+
+[[package]]
+name = "serde_derive"
+version = "1.0.133"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ed201699328568d8d08208fdd080e3ff594e6c422e438b6705905da01005d537"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "serde_json"
+version = "1.0.74"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ee2bb9cd061c5865d345bb02ca49fcef1391741b672b54a0bf7b679badec3142"
+dependencies = [
+ "itoa",
+ "ryu",
+ "serde",
+]
+
+[[package]]
+name = "shlex"
+version = "0.1.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7fdf1b9db47230893d76faad238fd6097fd6d6a9245cd7a4d90dbd639536bbd2"
+
+[[package]]
+name = "simplelog"
+version = "0.11.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ecabc0118918611790b8615670ab79296272cbe09496b6884b02b1e929c20886"
+dependencies = [
+ "chrono",
+ "log",
+ "termcolor",
+]
+
+[[package]]
+name = "smallvec"
+version = "1.7.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1ecab6c735a6bb4139c0caafd0cc3635748bbb3acf4550e8138122099251f309"
+
+[[package]]
+name = "spin"
+version = "0.5.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6e63cff320ae2c57904679ba7cb63280a3dc4613885beafb148ee7bf9aa9042d"
+
+[[package]]
+name = "strsim"
+version = "0.8.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8ea5119cdb4c55b55d432abb513a0429384878c15dde60cc77b1c99de1a95a6a"
+
+[[package]]
+name = "strsim"
+version = "0.10.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "73473c0e59e6d5812c5dfe2a064a6444949f089e20eec9a2e5506596494e4623"
+
+[[package]]
+name = "syn"
+version = "1.0.85"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a684ac3dcd8913827e18cd09a68384ee66c1de24157e3c556c9ab16d85695fb7"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "unicode-xid",
+]
+
+[[package]]
+name = "termcolor"
+version = "1.1.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2dfed899f0eb03f32ee8c6a0aabdb8a7949659e3466561fc0adf54e26d88c5f4"
+dependencies = [
+ "winapi-util",
+]
+
+[[package]]
+name = "terminal_size"
+version = "0.1.17"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "633c1a546cee861a1a6d0dc69ebeca693bf4296661ba7852b9d21d159e0506df"
+dependencies = [
+ "libc",
+ "winapi",
+]
+
+[[package]]
+name = "textwrap"
+version = "0.11.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d326610f408c7a4eb6f51c37c330e496b08506c9457c9d34287ecc38809fb060"
+dependencies = [
+ "unicode-width",
+]
+
+[[package]]
+name = "textwrap"
+version = "0.14.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0066c8d12af8b5acd21e00547c3797fde4e8677254a7ee429176ccebbe93dd80"
+
+[[package]]
+name = "thiserror"
+version = "1.0.30"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "854babe52e4df1653706b98fcfc05843010039b406875930a70e4d9644e5c417"
+dependencies = [
+ "thiserror-impl",
+]
+
+[[package]]
+name = "thiserror-impl"
+version = "1.0.30"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "aa32fd3f627f367fe16f893e2597ae3c05020f8bba2666a4e6ea73d377e5714b"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "time"
+version = "0.1.43"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ca8a50ef2360fbd1eeb0ecd46795a87a19024eb4b53c5dc916ca1fd95fe62438"
+dependencies = [
+ "libc",
+ "winapi",
+]
+
+[[package]]
+name = "tinyvec"
+version = "1.5.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2c1c1d5a42b6245520c249549ec267180beaffcc0615401ac8e31853d4b6d8d2"
+dependencies = [
+ "tinyvec_macros",
+]
+
+[[package]]
+name = "tinyvec_macros"
+version = "0.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "cda74da7e1a664f795bb1f8a87ec406fb89a02522cf6e50620d016add6dbbf5c"
+
+[[package]]
+name = "toml"
+version = "0.5.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a31142970826733df8241ef35dc040ef98c679ab14d7c3e54d827099b3acecaa"
+dependencies = [
+ "serde",
+]
+
+[[package]]
+name = "tstr"
+version = "0.2.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5e557019b23bfc6bf04d4b320d8e65186bc793489c4cdc5ebdd345770256aeaa"
+dependencies = [
+ "tstr_proc_macros",
+]
+
+[[package]]
+name = "tstr_proc_macros"
+version = "0.2.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e78122066b0cb818b8afd08f7ed22f7fdbc3e90815035726f0840d0d26c0747a"
+
+[[package]]
+name = "typed-arena"
+version = "2.0.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0685c84d5d54d1c26f7d3eb96cd41550adb97baed141a761cf335d3d33bcd0ae"
+
+[[package]]
+name = "unicode-bidi"
+version = "0.3.7"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1a01404663e3db436ed2746d9fefef640d868edae3cceb81c3b8d5732fda678f"
+
+[[package]]
+name = "unicode-normalization"
+version = "0.1.19"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d54590932941a9e9266f0832deed84ebe1bf2e4c9e4a3554d393d18f5e854bf9"
+dependencies = [
+ "tinyvec",
+]
+
+[[package]]
+name = "unicode-width"
+version = "0.1.9"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3ed742d4ea2bd1176e236172c8429aaf54486e7ac098db29ffe6529e0ce50973"
+
+[[package]]
+name = "unicode-xid"
+version = "0.2.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8ccb82d61f80a663efe1f787a51b16b5a51e3314d6ac365b08639f52387b33f3"
+
+[[package]]
+name = "untrusted"
+version = "0.7.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a156c684c91ea7d62626509bce3cb4e1d9ed5c4d978f7b4352658f96a4c26b4a"
+
+[[package]]
+name = "ureq"
+version = "2.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9399fa2f927a3d327187cbd201480cee55bee6ac5d3c77dd27f0c6814cff16d5"
+dependencies = [
+ "base64",
+ "chunked_transfer",
+ "flate2",
+ "log",
+ "once_cell",
+ "rustls",
+ "url",
+ "webpki",
+ "webpki-roots",
+]
+
+[[package]]
+name = "url"
+version = "2.2.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a507c383b2d33b5fc35d1861e77e6b383d158b2da5e14fe51b83dfedf6fd578c"
+dependencies = [
+ "form_urlencoded",
+ "idna",
+ "matches",
+ "percent-encoding",
+]
+
+[[package]]
+name = "uuid"
+version = "0.8.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "bc5cf98d8186244414c848017f0e2676b3fcb46807f6668a97dfe67359a3c4b7"
+
+[[package]]
+name = "vec_map"
+version = "0.8.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f1bddf1187be692e79c5ffeab891132dfb0f236ed36a43c7ed39f1165ee20191"
+
+[[package]]
+name = "version_check"
+version = "0.9.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "49874b5167b65d7193b8aba1567f5c7d93d001cafc34600cee003eda787e483f"
+
+[[package]]
+name = "volatile"
+version = "0.4.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e4c2dbd44eb8b53973357e6e207e370f0c1059990df850aca1eca8947cf464f0"
+
+[[package]]
+name = "wasi"
+version = "0.10.2+wasi-snapshot-preview1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "fd6fbd9a79829dd1ad0cc20627bf1ed606756a7f77edff7b66b7064f9cb327c6"
+
+[[package]]
+name = "wasm-bindgen"
+version = "0.2.78"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "632f73e236b219150ea279196e54e610f5dbafa5d61786303d4da54f84e47fce"
+dependencies = [
+ "cfg-if 1.0.0",
+ "wasm-bindgen-macro",
+]
+
+[[package]]
+name = "wasm-bindgen-backend"
+version = "0.2.78"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a317bf8f9fba2476b4b2c85ef4c4af8ff39c3c7f0cdfeed4f82c34a880aa837b"
+dependencies = [
+ "bumpalo",
+ "lazy_static",
+ "log",
+ "proc-macro2",
+ "quote",
+ "syn",
+ "wasm-bindgen-shared",
+]
+
+[[package]]
+name = "wasm-bindgen-macro"
+version = "0.2.78"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d56146e7c495528bf6587663bea13a8eb588d39b36b679d83972e1a2dbbdacf9"
+dependencies = [
+ "quote",
+ "wasm-bindgen-macro-support",
+]
+
+[[package]]
+name = "wasm-bindgen-macro-support"
+version = "0.2.78"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7803e0eea25835f8abdc585cd3021b3deb11543c6fe226dcd30b228857c5c5ab"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+ "wasm-bindgen-backend",
+ "wasm-bindgen-shared",
+]
+
+[[package]]
+name = "wasm-bindgen-shared"
+version = "0.2.78"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0237232789cf037d5480773fe568aac745bfe2afbc11a863e97901780a6b47cc"
+
+[[package]]
+name = "web-sys"
+version = "0.3.55"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "38eb105f1c59d9eaa6b5cdc92b859d85b926e82cb2e0945cd0c9259faa6fe9fb"
+dependencies = [
+ "js-sys",
+ "wasm-bindgen",
+]
+
+[[package]]
+name = "webpki"
+version = "0.22.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f095d78192e208183081cc07bc5515ef55216397af48b873e5edcd72637fa1bd"
+dependencies = [
+ "ring",
+ "untrusted",
+]
+
+[[package]]
+name = "webpki-roots"
+version = "0.22.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "552ceb903e957524388c4d3475725ff2c8b7960922063af6ce53c9a43da07449"
+dependencies = [
+ "webpki",
+]
+
+[[package]]
+name = "which"
+version = "3.1.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d011071ae14a2f6671d0b74080ae0cd8ebf3a6f8c9589a2cd45f23126fe29724"
+dependencies = [
+ "libc",
+]
+
+[[package]]
+name = "widestring"
+version = "0.5.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "17882f045410753661207383517a6f62ec3dbeb6a4ed2acce01f0728238d1983"
+
+[[package]]
+name = "winapi"
+version = "0.3.9"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5c839a674fcd7a98952e593242ea400abe93992746761e38641405d28b00f419"
+dependencies = [
+ "winapi-i686-pc-windows-gnu",
+ "winapi-x86_64-pc-windows-gnu",
+]
+
+[[package]]
+name = "winapi-i686-pc-windows-gnu"
+version = "0.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ac3b87c63620426dd9b991e5ce0329eff545bccbbb34f3be09ff6fb6ab51b7b6"
+
+[[package]]
+name = "winapi-util"
+version = "0.1.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "70ec6ce85bb158151cae5e5c87f95a8e97d2c0c4b001223f33a334e3ce5de178"
+dependencies = [
+ "winapi",
+]
+
+[[package]]
+name = "winapi-x86_64-pc-windows-gnu"
+version = "0.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "712e227841d057c1ee1cd2fb22fa7e5a5461ae8e48fa2ca79ec42cfc1931183f"
+
+[[package]]
+name = "x86_64"
+version = "0.14.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "bbc6ed1ed2cd4536b083c34041aff7b84448ee25ac4aa5e9d54802ce226f9815"
+dependencies = [
+ "bit_field",
+ "bitflags",
+ "volatile",
+]

From 3527b2f81033d6c394503dcc8ea5bcf688e02980 Mon Sep 17 00:00:00 2001
From: ko1N <ko1N1337@gmail.com>
Date: Sun, 13 Feb 2022 23:51:56 +0100
Subject: [PATCH 24/24] Bumped version to 0.2.0-beta1

---
 Cargo.lock                  | 31 +++++++++++++++++++------------
 leechcore-sys/Cargo.toml    |  3 ++-
 memflow-pcileech/Cargo.toml |  9 +++++----
 3 files changed, 26 insertions(+), 17 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index cd15928..99a0d47 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -190,7 +190,8 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
 [[package]]
 name = "cglue"
 version = "0.2.5"
-source = "git+https://github.com/h33p/cglue.git?branch=main#02e0f1089fe942edcda0391d12a008b6459bcc99"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9537a13fdbce0f3ef3fbc55d70dfd93c807c9c71fbdf97950da033ab1ef5a5ad"
 dependencies = [
  "abi_stable",
  "cglue-macro",
@@ -200,8 +201,9 @@ dependencies = [
 
 [[package]]
 name = "cglue-gen"
-version = "0.2.2"
-source = "git+https://github.com/h33p/cglue.git?branch=main#02e0f1089fe942edcda0391d12a008b6459bcc99"
+version = "0.2.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8693afab1b06d4722b35d51bc4c4ea7a41887e3f95ad4a67b73bb82cf7efe7c1"
 dependencies = [
  "itertools",
  "lazy_static",
@@ -214,7 +216,8 @@ dependencies = [
 [[package]]
 name = "cglue-macro"
 version = "0.2.1"
-source = "git+https://github.com/h33p/cglue.git?branch=main#02e0f1089fe942edcda0391d12a008b6459bcc99"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5a29a3b995b31756072458741810fd9ffe73b0a5fafa6ad08324b463c44ef528"
 dependencies = [
  "cglue-gen",
  "proc-macro2",
@@ -635,7 +638,7 @@ checksum = "830d08ce1d1d941e6b30645f1a0eb5643013d835ce3779a5fc208261dbe10f55"
 
 [[package]]
 name = "leechcore-sys"
-version = "0.1.5"
+version = "0.2.0-beta1"
 dependencies = [
  "bindgen",
  "cc",
@@ -691,8 +694,9 @@ checksum = "308cc39be01b73d0d18f82a0e7b2a3df85245f84af96fdddc5d202d27e47b86a"
 
 [[package]]
 name = "memflow"
-version = "0.1.5"
-source = "git+https://github.com/memflow/memflow?branch=next#8627a9d575206461bec2b9c236a80af4879259e3"
+version = "0.2.0-beta1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b4bd4a071d4376feb60428ba6e19f43174e992a32bf4056a8e1ac56347096696"
 dependencies = [
  "abi_stable",
  "bitflags",
@@ -711,6 +715,7 @@ dependencies = [
  "memmap",
  "no-std-compat",
  "once_cell",
+ "pelite",
  "rangemap",
  "serde",
  "smallvec",
@@ -720,8 +725,9 @@ dependencies = [
 
 [[package]]
 name = "memflow-derive"
-version = "0.1.5"
-source = "git+https://github.com/memflow/memflow?branch=next#8627a9d575206461bec2b9c236a80af4879259e3"
+version = "0.2.0-beta1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b162b846355c1067a2f83fb37e193a441d05d6528e02d9bab658becbb78851fb"
 dependencies = [
  "darling",
  "proc-macro-crate",
@@ -732,7 +738,7 @@ dependencies = [
 
 [[package]]
 name = "memflow-pcileech"
-version = "0.1.5"
+version = "0.2.0-beta1"
 dependencies = [
  "clap 3.0.5",
  "leechcore-sys",
@@ -744,8 +750,9 @@ dependencies = [
 
 [[package]]
 name = "memflow-win32"
-version = "0.1.5"
-source = "git+https://github.com/memflow/memflow-win32?branch=main#e94c7120296b0fc0404fe79b41f87f646362c28e"
+version = "0.2.0-beta1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d399458de5a5884fbb8cc1ddebad74845275d6a58d98a4ade0caeca12380c5a3"
 dependencies = [
  "dirs",
  "goblin",
diff --git a/leechcore-sys/Cargo.toml b/leechcore-sys/Cargo.toml
index da07684..7e81e48 100644
--- a/leechcore-sys/Cargo.toml
+++ b/leechcore-sys/Cargo.toml
@@ -1,10 +1,11 @@
 [package]
 name = "leechcore-sys"
-version = "0.1.5"
+version = "0.2.0-beta1"
 authors = ["ko1N <ko1N1337@gmail.com>"]
 edition = "2018"
 readme = "../README.md"
 license-file = "../LICENSE"
+license = "GPL-3.0"
 
 links = "leechcore"
 
diff --git a/memflow-pcileech/Cargo.toml b/memflow-pcileech/Cargo.toml
index 2e9f530..d6397f3 100644
--- a/memflow-pcileech/Cargo.toml
+++ b/memflow-pcileech/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "memflow-pcileech"
-version = "0.1.5"
+version = "0.2.0-beta1"
 authors = ["ko1N <ko1N1337@gmail.com>"]
 edition = "2018"
 description = "qemu procfs connector for leechcore/pcileech"
@@ -9,6 +9,7 @@ readme = "../README.md"
 homepage = "https://memflow.github.io"
 repository = "https://github.com/memflow/memflow-pcileech"
 license-file = "../LICENSE"
+license = "GPL-3.0"
 keywords = [ "memflow", "introspection", "memory" ]
 categories = [ "api-bindings", "memory-management", "os" ]
 
@@ -16,14 +17,14 @@ categories = [ "api-bindings", "memory-management", "os" ]
 crate-type = ["lib", "cdylib"]
 
 [dependencies]
-memflow = { git = "https://github.com/memflow/memflow", branch = "next", features = ["plugins", "memmapfiles"] }
-leechcore-sys = { path = "../leechcore-sys" }
+memflow = { version = "^0.2.0-beta", features = ["plugins", "memmapfiles"] }
+leechcore-sys = { version = "0.2.0-beta1", path = "../leechcore-sys" }
 log = "^0.4.14"
 
 [dev-dependencies]
 clap = { version = "^3.0.5", features = ["cargo"] }
 simplelog = "^0.11.1"
-memflow-win32 = { git = "https://github.com/memflow/memflow-win32", branch = "main" }
+memflow-win32 = { version = "^0.2.0-beta" }
 
 [[example]]
 name = "read_phys"