diff --git a/Cargo.lock b/Cargo.lock
index cfbc20b..ebffc3b 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -189,9 +189,9 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
 
 [[package]]
 name = "cglue"
-version = "0.2.10"
+version = "0.2.11"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "15d7ac3d7a04e9aa5fdcd74126bed0217e3b9064dc55883fc1af63caffe07267"
+checksum = "8a83ef0a0d6f7a8db45b93b31fde7058968d9ec7aea2d9777413f30a6c82b69e"
 dependencies = [
  "abi_stable",
  "cglue-macro",
@@ -1517,9 +1517,9 @@ dependencies = [
 
 [[package]]
 name = "which"
-version = "4.2.4"
+version = "4.2.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2a5a7e487e921cf220206864a94a89b6c6905bfc19f1057fa26a4cb360e5c1d2"
+checksum = "5c4fb54e6113b6a8772ee41c3404fb0301ac79604489467e0a9ce1f3e97c24ae"
 dependencies = [
  "either",
  "lazy_static",
diff --git a/memflow-pcileech/src/lib.rs b/memflow-pcileech/src/lib.rs
index a475ff2..47851f2 100644
--- a/memflow-pcileech/src/lib.rs
+++ b/memflow-pcileech/src/lib.rs
@@ -116,8 +116,8 @@ struct WriteGap {
 }
 
 impl PhysicalMemory for PciLeech {
-    fn phys_read_raw_iter<'a>(&mut self, data: PhysicalReadMemOps) -> Result<()> {
-        let vec = if let Some(mem_map) = &self.mem_map {
+    fn phys_read_raw_iter<'a>(&mut self, mut data: PhysicalReadMemOps) -> Result<()> {
+        let mut vec = if let Some(mem_map) = &self.mem_map {
             mem_map
                 .map_iter(data.inp, data.out_fail)
                 .map(|d| (d.0 .0.into(), d.1, d.2))
@@ -149,8 +149,8 @@ impl PhysicalMemory for PciLeech {
         // prepare mems
         let mut gaps = Vec::new();
         let mut i = 0usize;
-        for read in vec.into_iter() {
-            for (page_addr, out) in read.2.page_chunks(read.0.into(), PAGE_SIZE) {
+        for (addr, _, out) in vec.iter_mut() {
+            for (page_addr, out) in CSliceMut::from(out).page_chunks(addr.address(), PAGE_SIZE) {
                 let mem = unsafe { *mems.add(i) };
 
                 let addr_align = page_addr.to_umem() & (BUF_ALIGN - 1);
@@ -235,18 +235,15 @@ impl PhysicalMemory for PciLeech {
         };
 
         // call out sucess for everything
-        /*
-        for read in vec.into_iter() {
-            for (page_addr, out) in read.2.page_chunks(read.0.into(), PAGE_SIZE) {
-                opt_call(data.out.as_deref_mut(), CTup2(page_addr, out));
-            }
+        // TODO: implement proper callback based on `f` in scatter
+        for (_, meta_addr, out) in vec.into_iter() {
+            opt_call(data.out.as_deref_mut(), CTup2(meta_addr, out));
         }
-        */
 
         Ok(())
     }
 
-    fn phys_write_raw_iter<'a>(&mut self, data: PhysicalWriteMemOps) -> Result<()> {
+    fn phys_write_raw_iter<'a>(&mut self, mut data: PhysicalWriteMemOps) -> Result<()> {
         let vec = if let Some(mem_map) = &self.mem_map {
             mem_map
                 .map_iter(data.inp, data.out_fail)
@@ -383,6 +380,12 @@ impl PhysicalMemory for PciLeech {
             LcMemFree(mems as *mut c_void);
         };
 
+        // call out sucess for everything
+        // TODO: implement proper callback based on `f` in scatter
+        for (_, meta_addr, out) in vec.into_iter() {
+            opt_call(data.out.as_deref_mut(), CTup2(meta_addr, out));
+        }
+
         Ok(())
     }