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79 lines
2.3 KiB
Coq
79 lines
2.3 KiB
Coq
8 months ago
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// 本次实验, 是通过fifo的自己例化的两个功能模块, 通过这两个功能模块 控制fifo的ip核实验
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// 写模块: 在写功能可用之后, 判断是否是空的, 如果是空的, 就持续写直到写满
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// 读模块: 写功能写满之后, 取数据, 只到获取完毕
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// 注意本实验 读和写实不同的时钟域, 是否可读写, 需要通过打拍判断外部时钟域的值
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// 判断即将写满/即将为空时, 要注意时钟周期, 能给出状态1, 说明上上个周期的一次写入导致快满/空了
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// 上个周期再当前周期如果继续进行操作, 虽然 这个标志位还没转变为0, 但是他实际内部已经是full或者emtpy了, 再写就溢出了
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module test_fifo(
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input wire sys_clk, // U18
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input wire sys_rst //J15
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);
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wire clk_100m;
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wire clk_50m;
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wire locked;
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wire logic_rst;
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assign logic_rst = sys_rst && locked; // 需要在高电平(按下并弹开按钮) 之后且 时钟稳定之后对子模块进行逻辑复位
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wire is_empty;
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wire is_almost_full;
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wire is_wr_rst_busy;
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wire fifo_wr_en;
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wire fifo_wr_data;
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fifo_wr u_fifo_wr(
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.wr_clk(clk_50m),
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.rst(logic_rst),
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.is_empty(is_empty),
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.is_almost_full(is_almost_full),
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.is_wr_rst_busy(is_wr_rst_busy),
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.fifo_wr_en(fifo_wr_en),
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.fifo_wr_data(fifo_wr_data)
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);
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wire is_full;
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wire is_almost_empty;
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wire is_rd_rst_busy;
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wire fifo_rd_en;
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wire fifo_rd_data;
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fifo_rd u_fifo_rd(
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.rd_clk(clk_100m),
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.rst(logic_rst),
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.is_full(is_full),
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.is_almost_empty(is_almost_empty),
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.is_rd_rst_busy(is_rd_rst_busy),
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.fifo_rd_en(fifo_rd_en),
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.fifo_rd_data(fifo_rd_data)
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);
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clk_wiz_0 u_clk_wiz_0(
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.clk_in1(sys_clk),
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.clk_out1(clk_100m),
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.clk_out2(clk_50m),
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.locked(locked)
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);
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wire [7:0]rd_data_count;
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wire [7:0]wr_data_count;
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fifo_generator_0 u_fifo_generator_0(
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.rst(~logic_rst), // 该ip核内是高电平时钟信号有效, 平时需要低电平, 我们取logic_rst(这个是高电平)反
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.wr_clk(clk_50m),
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.rd_clk(clk_100m),
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.din(fifo_wr_data),
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.wr_en(fifo_wr_en),
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.rd_en(fifo_rd_en),
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.dout(fifo_rd_data),
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.full(is_full),
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.almost_full(is_almost_empty),
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.rd_data_count(rd_data_count),
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.wr_data_count(wr_data_count),
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.wr_rst_busy(is_wr_rst_busy),
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.rd_rst_busy(is_rd_rst_busy)
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);
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endmodule
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