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47 lines
1.1 KiB
Coq
47 lines
1.1 KiB
Coq
8 months ago
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// 该模块会在写满了fifo之后, 开始读, 直到读空
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module fifo_rd(
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input rd_clk,
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input rst,
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input [7:0] fifo_rd_data, // fifo 读到的数据
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input is_full, // 是否写满了, 这个是 写时钟域的信号
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input is_almost_empty, // 快空了
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input is_rd_rst_busy, // 是否正在初始化读
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output reg fifo_rd_en // 是否能够读了
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);
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reg is_full_0;
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reg is_full_1;
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always @(posedge rd_clk or negedge rst) begin
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if (!rst) begin
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is_full_0 <= 1'b0;
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is_full_1 <= 1'b0;
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end
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else begin
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is_full_0 <= is_full;
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is_full_1 <= is_full_0;
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end
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end
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// 控制是否可读
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always @(posedge rd_clk or negedge rst) begin
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if (!rst) begin
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fifo_rd_en <= 1'b0;
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end
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else if (!is_rd_rst_busy) begin // 功能已经准备就绪
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if (is_full_1) begin // 打两拍确定是满的, 在进行读取
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fifo_rd_en <= 1'b1;
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end
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else if(is_almost_empty) begin // 上个时钟周期快空了, 其实当前时钟周期已经空了
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fifo_rd_en <= 1'b0;
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end
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else begin
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end
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end
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else begin
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end
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end
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endmodule
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