yanguangshaonian
/
verilog_stu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
verilog_stu/.vscode/settings.json

4 lines
96 B
JSON
Raw Normal View History Unescape Escape

增加一下项目文件
{
移位数码管, 仿真通过啦~
"digital-ide.welcome.show": false,
"digital-ide.dont-show-again.propose.issue": true
增加一下项目文件
}