verilog_stu/digital_tube/tb_dt.v

`timescale 1ns/1ns
module tb_dt();

reg sys_clk;
reg sys_rst;

initial begin
    sys_clk <= 1'b0;
    // 复位
    sys_rst <= 1'b0;
    #200
    // 结束复位
    sys_rst <= 1'b1;
end

// 每20ns 产生一个时钟周期, 所以需要10ns 翻转一次
always #10 sys_clk = ~sys_clk;


reg [25:0] CNT;

always @(posedge sys_clk or negedge sys_rst) begin
    if (sys_rst == 1'b0) begin
        CNT <= 25'd0;
    end
    else if (CNT < (25'd25 - 25'd1)) begin
        CNT <= CNT + 25'd1;
    end
    else begin
        CNT <= 25'b0;
    end
end



reg [7:0] data;
always @(posedge sys_clk or negedge sys_rst) begin
    if (sys_rst == 1'b0) begin 
        data <= 8'b1_00_0_0000;
    end
    else if (CNT == (25'd25 - 25'd1)) begin
        data[3:0] <= data[3:0] + 4'b1;
        data[6:5] <= data[6:5] + 2'b1;
    end
    else begin

    end
end


wire [7:0] D;
wire [3:0] S;

dt u_dt(
    .data (data),
    .A (D[0]),
    .B (D[1]),
    .C (D[2]),
    .D (D[3]),
    .E (D[4]),
    .F (D[5]),
    .G (D[6]),
    .DP (D[7]),
    .S1 (S[0]),
    .S2 (S[1]),
    .S3 (S[2]),
    .S4 (S[3])
);

endmodule