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220 lines
8.3 KiB
Systemverilog
220 lines
8.3 KiB
Systemverilog
8 months ago
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module fpga_top (
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output wire o_led0,
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input wire i_pcie_rstn,
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input wire i_pcie_refclkp, i_pcie_refclkn,
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input wire [0:0] i_pcie_rxp, i_pcie_rxn,
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output wire [0:0] o_pcie_txp, o_pcie_txn
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);
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localparam AXI_IDWIDTH = 4;
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localparam AXI_AWIDTH = 64;
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localparam AXI_DWIDTH = 64;
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wire pcie_rstn;
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wire pcie_refclk;
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wire rstn;
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wire clk;
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// PCIe XDMA's AXI interface
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////
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wire axi_awready;
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wire axi_awvalid;
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wire [ AXI_AWIDTH-1:0] axi_awaddr;
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wire [ 7:0] axi_awlen;
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wire [ AXI_IDWIDTH-1:0] axi_awid;
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// AXI Master Write Data Channel
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wire axi_wready;
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wire axi_wvalid;
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wire axi_wlast;
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wire [ AXI_DWIDTH-1:0] axi_wdata;
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wire [(AXI_DWIDTH/8)-1:0] axi_wstrb;
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// AXI Master Write Response Channel
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wire axi_bready;
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wire axi_bvalid;
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wire [ AXI_IDWIDTH-1:0] axi_bid;
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wire [ 1:0] axi_bresp;
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// AXI Master Read Address Channel
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wire axi_arready;
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wire axi_arvalid;
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wire [ AXI_AWIDTH-1:0] axi_araddr;
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wire [ 7:0] axi_arlen;
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wire [ AXI_IDWIDTH-1:0] axi_arid;
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// AXI Master Read Data Channel
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wire axi_rready;
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wire axi_rvalid;
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wire axi_rlast;
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wire [ AXI_DWIDTH-1:0] axi_rdata;
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wire [ AXI_IDWIDTH-1:0] axi_rid;
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wire [ 1:0] axi_rresp;
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Ref clock input buffer
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////
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IBUFDS_GTE2 refclk_ibuf (
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.CEB ( 1'b0 ),
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.I ( i_pcie_refclkp ),
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.IB ( i_pcie_refclkn ),
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.O ( pcie_refclk ),
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.ODIV2 ( )
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);
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Reset input buffer
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////
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IBUF sys_reset_n_ibuf (
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.I ( i_pcie_rstn ),
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.O ( pcie_rstn )
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);
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// PCIe XDMA core
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////
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xdma_0 xdma_0_i (
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// PCI Express (PCIe) Interface : connect to the pins of FPGA chip
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.sys_rst_n ( pcie_rstn ),
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.sys_clk ( pcie_refclk ),
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.pci_exp_txn ( o_pcie_txn ),
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.pci_exp_txp ( o_pcie_txp ),
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.pci_exp_rxn ( i_pcie_rxn ),
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.pci_exp_rxp ( i_pcie_rxp ),
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// PCIe link up
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.user_lnk_up ( o_led0 ),
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// interrupts
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.usr_irq_req ( 16'h0 ),
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.usr_irq_ack ( ),
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//
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.msix_enable ( ),
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// clock/reset for user (for AXI)
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.axi_aclk ( clk ),
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.axi_aresetn ( rstn ),
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// AXI Interface
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.m_axi_awready ( axi_awready ),
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.m_axi_awvalid ( axi_awvalid ),
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.m_axi_awaddr ( axi_awaddr ),
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.m_axi_awlen ( axi_awlen ),
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.m_axi_awid ( axi_awid ),
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.m_axi_awsize ( ),
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.m_axi_awburst ( ),
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.m_axi_awprot ( ),
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.m_axi_awlock ( ),
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.m_axi_awcache ( ),
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.m_axi_wready ( axi_wready ),
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.m_axi_wvalid ( axi_wvalid ),
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.m_axi_wdata ( axi_wdata ),
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.m_axi_wstrb ( axi_wstrb ),
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.m_axi_wlast ( axi_wlast ),
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.m_axi_bready ( axi_bready ),
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.m_axi_bvalid ( axi_bvalid ),
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.m_axi_bid ( axi_bid ),
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.m_axi_bresp ( axi_bresp ),
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.m_axi_arready ( axi_arready ),
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.m_axi_arvalid ( axi_arvalid ),
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.m_axi_araddr ( axi_araddr ),
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.m_axi_arlen ( axi_arlen ),
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.m_axi_arid ( axi_arid ),
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.m_axi_arsize ( ),
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.m_axi_arburst ( ),
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.m_axi_arprot ( ),
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.m_axi_arlock ( ),
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.m_axi_arcache ( ),
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.m_axi_rready ( axi_rready ),
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.m_axi_rvalid ( axi_rvalid ),
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.m_axi_rlast ( axi_rlast ),
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.m_axi_rdata ( axi_rdata ),
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.m_axi_rid ( axi_rid ),
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.m_axi_rresp ( axi_rresp ),
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// AXI bypass interface
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.m_axib_awready ( '0 ),
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.m_axib_awvalid ( ),
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.m_axib_awaddr ( ),
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.m_axib_awlen ( ),
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.m_axib_awid ( ),
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.m_axib_awsize ( ),
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.m_axib_awburst ( ),
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.m_axib_awprot ( ),
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.m_axib_awlock ( ),
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.m_axib_awcache ( ),
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.m_axib_wready ( '0 ),
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.m_axib_wvalid ( ),
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.m_axib_wlast ( ),
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.m_axib_wdata ( ),
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.m_axib_wstrb ( ),
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.m_axib_bready ( ),
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.m_axib_bvalid ( '0 ),
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.m_axib_bid ( '0 ),
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.m_axib_bresp ( '0 ),
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.m_axib_arready ( '0 ),
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.m_axib_arvalid ( ),
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.m_axib_araddr ( ),
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.m_axib_arlen ( ),
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.m_axib_arid ( ),
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.m_axib_arsize ( ),
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.m_axib_arburst ( ),
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.m_axib_arprot ( ),
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.m_axib_arlock ( ),
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.m_axib_arcache ( ),
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.m_axib_rready ( ),
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.m_axib_rvalid ( '0 ),
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.m_axib_rlast ( '0 ),
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.m_axib_rdata ( '0 ),
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.m_axib_rid ( '0 ),
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.m_axib_rresp ( '0 )
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);
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// AXI BRAM connected to PCIe XDMA's AXI interface
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////
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axi_bram #(
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.AXI_IDWIDTH ( AXI_IDWIDTH ),
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.AXI_AWIDTH ( AXI_AWIDTH ),
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.AXI_DWIDTH ( AXI_DWIDTH ),
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.MEM_AWIDTH ( 14 ) // BRAM size = MEM_AWIDTH*AXI_DWIDTH (bits) = MEM_AWIDTH*AXI_DWIDTH/8 (bytes)
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) axi_bram_i (
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.rstn ( rstn ),
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.clk ( clk ),
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// AXI Memory Mapped interface
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.s_axi_awready ( axi_awready ),
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.s_axi_awvalid ( axi_awvalid ),
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.s_axi_awaddr ( axi_awaddr ),
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.s_axi_awlen ( axi_awlen ),
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.s_axi_awid ( axi_awid ),
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.s_axi_wready ( axi_wready ),
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.s_axi_wvalid ( axi_wvalid ),
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.s_axi_wlast ( axi_wlast ),
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.s_axi_wdata ( axi_wdata ),
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.s_axi_wstrb ( axi_wstrb ),
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.s_axi_bready ( axi_bready ),
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.s_axi_bvalid ( axi_bvalid ),
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.s_axi_bid ( axi_bid ),
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.s_axi_bresp ( axi_bresp ),
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.s_axi_arready ( axi_arready ),
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.s_axi_arvalid ( axi_arvalid ),
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.s_axi_araddr ( axi_araddr ),
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.s_axi_arlen ( axi_arlen ),
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.s_axi_arid ( axi_arid ),
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.s_axi_rready ( axi_rready ),
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.s_axi_rvalid ( axi_rvalid ),
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.s_axi_rlast ( axi_rlast ),
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.s_axi_rdata ( axi_rdata ),
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.s_axi_rid ( axi_rid ),
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.s_axi_rresp ( axi_rresp )
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);
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endmodule
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// 1000_0000_0000_0000_0000
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