diff --git a/led_matrix/key.v b/led_matrix/key.v new file mode 100644 index 0000000..f1fa483 --- /dev/null +++ b/led_matrix/key.v @@ -0,0 +1,164 @@ +module key_1( + input wire sys_clk, // U18 + input wire sys_rst, //J15 + // d20,d19,b19,a20 + output reg c4, c3, c2, c1, + // f16.f17,e18,e19 + output reg r4, r3, r2, r1, + + // f20 f19 b20 c20 j16 k16 m18 m17 l17 l16 l15 l14 m15 m14 n16 n15 + // x4 x2 x1 x3 x6 x7 x5 x8 + // y2 y3 y5 y8 y7 y1 y6 y4 + output wire o1, o2, o3, o4, o5, o6, o7, o8, o16,o15,o14,o13,o12,o11,o10,o9 +); +reg [7:0] KEY_CODE; + +parameter GET_START = 4'b0010; +parameter GET_ROW = 4'b0010; +parameter GET_COL = 4'b0100; +parameter GET_END = 4'b1000; +reg STATUS = 4'b0000; + + +always @(posedge sys_clk or negedge sys_rst) begin + if (sys_rst == 1'b0) begin + STATUS <= GET_START; + end + else begin + end +end + + +// 每个时钟周期�?查行 +always @(posedge sys_clk or negedge sys_rst) begin + // todo �?查锁 + // todo 可能会一次按多个按键, 后面再处理吧 + if (STATUS == GET_START) begin + STATUS <= GET_ROW; + {c4, c3, c2, c1} <= 4'b1111; + {r4, r3, r2, r1} <= 4'b0000; + KEY_CODE <= 8'b00000000; + end + else if (STATUS == GET_ROW && {c4, c3, c2, c1} != 4'b1111) begin + KEY_CODE[7:4] <= {c4, c3, c2, c1}; + STATUS <= GET_COL; + + {c4, c3, c2, c1} <= 4'b0000; + {r4, r3, r2, r1} <= 4'b1111; + end + else if (STATUS == GET_COL && {r4, r3, r2, r1} != 4'b1111) begin + KEY_CODE[3:0] <= {r4, r3, r2, r1}; + STATUS <= GET_END; + end + else if (STATUS == GET_END) begin + STATUS <= GET_START; + end + else begin + end +end + + +reg [7:0] x; +reg [7:0] y; +always @(posedge sys_clk or negedge sys_rst) begin + if (sys_rst == 1'b0) begin + x <= 8'b0000_0000; + end + else begin + end + + case (KEY_CODE) + 8'b1110_1110: begin + x <= 8'b0000_0001; + y <= 8'b0000_0001; + end + 8'b1110_1101: begin + x <= 8'b0000_0010; + y <= 8'b0000_0001; + end + 8'b1110_1011: begin + x <= 8'b0000_0100; + y <= 8'b0000_0001; + end + 8'b1110_0111: begin + x <= 8'b0000_1000; + y <= 8'b0000_0001; + end + + 8'b1101_1110: begin + x <= 8'b0001_0000; + y <= 8'b0000_0001; + end + 8'b1101_1101: begin + x <= 8'b0010_0000; + y <= 8'b0000_0001; + end + 8'b1101_1011: begin + x <= 8'b0100_0000; + y <= 8'b0000_0001; + end + 8'b1101_0111: begin + x <= 8'b1000_0000; + y <= 8'b0000_0001; + end + + 8'b1011_1110: begin + x <= 8'b0000_0001; + y <= 8'b0000_0010; + end + 8'b1011_1101: begin + x <= 8'b0000_0010; + y <= 8'b0000_0010; + end + 8'b1011_1011: begin + x <= 8'b0000_0100; + y <= 8'b0000_0010; + end + 8'b1011_0111: begin + x <= 8'b0000_1000; + y <= 8'b0000_0010; + end + + 8'b1011_1110: begin + x <= 8'b0001_0000; + y <= 8'b0000_0010; + end + 8'b1011_1101: begin + x <= 8'b0010_0000; + y <= 8'b0000_0010; + end + 8'b1011_1011: begin + x <= 8'b0100_0000; + y <= 8'b0000_0010; + end + 8'b1011_0111: begin + x <= 8'b1000_0000; + y <= 8'b0000_0010; + end + default: x <= 8'b0000_1000; + + endcase +end + +lm u_lm( + .x (x), + .y (y), + .o1 (o1), + .o2 (o2), + .o3 (o3), + .o4 (o4), + .o5 (o5), + .o6 (o6), + .o7 (o7), + .o8 (o8), + .o9 (o9), + .o10 (o10), + .o11 (o11), + .o12 (o12), + .o13 (o13), + .o14 (o14), + .o15 (o15), + .o16 (o16) +); + +endmodule \ No newline at end of file diff --git a/led_matrix/key.v.out b/led_matrix/key.v.out new file mode 100644 index 0000000..0d85f33 --- /dev/null +++ b/led_matrix/key.v.out @@ -0,0 +1,398 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "C:\iverilog\lib\ivl\system.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "C:\iverilog\lib\ivl\va_math.vpi"; +S_00000211009e6550 .scope module, "key" "key" 2 1; + .timescale 0 0; + .port_info 0 /INPUT 1 "sys_clk"; + .port_info 1 /INPUT 1 "sys_rst"; + .port_info 2 /OUTPUT 1 "c4"; + .port_info 3 /OUTPUT 1 "c3"; + .port_info 4 /OUTPUT 1 "c2"; + .port_info 5 /OUTPUT 1 "c1"; + .port_info 6 /OUTPUT 1 "r4"; + .port_info 7 /OUTPUT 1 "r3"; + .port_info 8 /OUTPUT 1 "r2"; + .port_info 9 /OUTPUT 1 "r1"; + .port_info 10 /OUTPUT 1 "A"; + .port_info 11 /OUTPUT 1 "B"; + .port_info 12 /OUTPUT 1 "C"; + .port_info 13 /OUTPUT 1 "D"; + .port_info 14 /OUTPUT 1 "E"; + .port_info 15 /OUTPUT 1 "F"; + .port_info 16 /OUTPUT 1 "G"; + .port_info 17 /OUTPUT 1 "DP"; + .port_info 18 /OUTPUT 1 "S1"; + .port_info 19 /OUTPUT 1 "S2"; + .port_info 20 /OUTPUT 1 "S3"; + .port_info 21 /OUTPUT 1 "S4"; +P_00000211009ebe70 .param/l "GET_COL" 0 2 16, C4<0100>; +P_00000211009ebea8 .param/l "GET_END" 0 2 17, C4<1000>; +P_00000211009ebee0 .param/l "GET_ROW" 0 2 15, C4<0010>; +P_00000211009ebf18 .param/l "GET_START" 0 2 14, C4<0010>; +o0000021100b79f88 .functor BUFZ 1, C4; HiZ drive +v00000211009eb120_0 .net "A", 0 0, o0000021100b79f88; 0 drivers +o0000021100b79fb8 .functor BUFZ 1, C4; HiZ drive +v00000211009eb9d0_0 .net "B", 0 0, o0000021100b79fb8; 0 drivers +o0000021100b79fe8 .functor BUFZ 1, C4; HiZ drive +v0000021100b56650_0 .net "C", 0 0, o0000021100b79fe8; 0 drivers +o0000021100b7a018 .functor BUFZ 1, C4; HiZ drive +v0000021100b60cf0_0 .net "D", 0 0, o0000021100b7a018; 0 drivers +o0000021100b7a048 .functor BUFZ 1, C4; HiZ drive +v0000021100b60d90_0 .net "DP", 0 0, o0000021100b7a048; 0 drivers +o0000021100b7a078 .functor BUFZ 1, C4; HiZ drive +v0000021100b60e30_0 .net "E", 0 0, o0000021100b7a078; 0 drivers +o0000021100b7a0a8 .functor BUFZ 1, C4; HiZ drive +v0000021100b60ed0_0 .net "F", 0 0, o0000021100b7a0a8; 0 drivers +o0000021100b7a0d8 .functor BUFZ 1, C4; HiZ drive +v0000021100b60f70_0 .net "G", 0 0, o0000021100b7a0d8; 0 drivers +v0000021100b61010_0 .var "KEY_CODE", 7 0; +o0000021100b7a138 .functor BUFZ 1, C4; HiZ drive +v0000021100b610b0_0 .net "S1", 0 0, o0000021100b7a138; 0 drivers +o0000021100b7a168 .functor BUFZ 1, C4; HiZ drive +v0000021100b61150_0 .net "S2", 0 0, o0000021100b7a168; 0 drivers +o0000021100b7a198 .functor BUFZ 1, C4; HiZ drive +v0000021100b611f0_0 .net "S3", 0 0, o0000021100b7a198; 0 drivers +o0000021100b7a1c8 .functor BUFZ 1, C4; HiZ drive +v0000021100b61290_0 .net "S4", 0 0, o0000021100b7a1c8; 0 drivers +v0000021100b61330_0 .var "STATUS", 0 0; +v0000021100b613d0_0 .var "c1", 0 0; +v0000021100b61560_0 .var "c2", 0 0; +v0000021100b61740_0 .var "c3", 0 0; +v0000021100b61f60_0 .var "c4", 0 0; +v0000021100b620a0_0 .var "r1", 0 0; +v0000021100b61c40_0 .var "r2", 0 0; +v0000021100b61920_0 .var "r3", 0 0; +v0000021100b61600_0 .var "r4", 0 0; +o0000021100b7a3a8 .functor BUFZ 1, C4; HiZ drive +v0000021100b62000_0 .net "sys_clk", 0 0, o0000021100b7a3a8; 0 drivers +o0000021100b7a3d8 .functor BUFZ 1, C4; HiZ drive +v0000021100b61d80_0 .net "sys_rst", 0 0, o0000021100b7a3d8; 0 drivers +v0000021100b62280_0 .var "x", 7 0; +v0000021100b61880_0 .var "y", 7 0; +E_0000021100b570c0/0 .event negedge, v0000021100b61d80_0; +E_0000021100b570c0/1 .event posedge, v0000021100b62000_0; +E_0000021100b570c0 .event/or E_0000021100b570c0/0, E_0000021100b570c0/1; + .scope S_00000211009e6550; +T_0 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000021100b61330_0, 0, 1; + %end; + .thread T_0; + .scope S_00000211009e6550; +T_1 ; + %wait E_0000021100b570c0; + %load/vec4 v0000021100b61d80_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_1.0, 4; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000021100b61330_0, 0; +T_1.0 ; + %jmp T_1; + .thread T_1; + .scope S_00000211009e6550; +T_2 ; + %wait E_0000021100b570c0; + %load/vec4 v0000021100b61330_0; + %pad/u 4; + %cmpi/e 2, 0, 4; + %jmp/0xz T_2.0, 4; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000021100b61330_0, 0; + %pushi/vec4 15, 0, 4; + %split/vec4 1; + %assign/vec4 v0000021100b613d0_0, 0; + %split/vec4 1; + %assign/vec4 v0000021100b61560_0, 0; + %split/vec4 1; + %assign/vec4 v0000021100b61740_0, 0; + %assign/vec4 v0000021100b61f60_0, 0; + %pushi/vec4 0, 0, 4; + %split/vec4 1; + %assign/vec4 v0000021100b620a0_0, 0; + %split/vec4 1; + %assign/vec4 v0000021100b61c40_0, 0; + %split/vec4 1; + %assign/vec4 v0000021100b61920_0, 0; + %assign/vec4 v0000021100b61600_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0000021100b61010_0, 0; + %jmp T_2.1; +T_2.0 ; + %load/vec4 v0000021100b61330_0; + %pad/u 4; + %cmpi/e 2, 0, 4; + %flag_get/vec4 4; + %jmp/0 T_2.4, 4; + %load/vec4 v0000021100b61f60_0; + %load/vec4 v0000021100b61740_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000021100b61560_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000021100b613d0_0; + %concat/vec4; draw_concat_vec4 + %pushi/vec4 15, 0, 4; + %cmp/ne; + %flag_get/vec4 4; + %and; +T_2.4; + %flag_set/vec4 8; + %jmp/0xz T_2.2, 8; + %load/vec4 v0000021100b61f60_0; + %load/vec4 v0000021100b61740_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000021100b61560_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000021100b613d0_0; + %concat/vec4; draw_concat_vec4 + %ix/load 4, 4, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0000021100b61010_0, 4, 5; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000021100b61330_0, 0; + %pushi/vec4 0, 0, 4; + %split/vec4 1; + %assign/vec4 v0000021100b613d0_0, 0; + %split/vec4 1; + %assign/vec4 v0000021100b61560_0, 0; + %split/vec4 1; + %assign/vec4 v0000021100b61740_0, 0; + %assign/vec4 v0000021100b61f60_0, 0; + %pushi/vec4 15, 0, 4; + %split/vec4 1; + %assign/vec4 v0000021100b620a0_0, 0; + %split/vec4 1; + %assign/vec4 v0000021100b61c40_0, 0; + %split/vec4 1; + %assign/vec4 v0000021100b61920_0, 0; + %assign/vec4 v0000021100b61600_0, 0; + %jmp T_2.3; +T_2.2 ; + %load/vec4 v0000021100b61330_0; + %pad/u 4; + %cmpi/e 4, 0, 4; + %flag_get/vec4 4; + %jmp/0 T_2.7, 4; + %load/vec4 v0000021100b61600_0; + %load/vec4 v0000021100b61920_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000021100b61c40_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000021100b620a0_0; + %concat/vec4; draw_concat_vec4 + %pushi/vec4 15, 0, 4; + %cmp/ne; + %flag_get/vec4 4; + %and; +T_2.7; + %flag_set/vec4 8; + %jmp/0xz T_2.5, 8; + %load/vec4 v0000021100b61600_0; + %load/vec4 v0000021100b61920_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000021100b61c40_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000021100b620a0_0; + %concat/vec4; draw_concat_vec4 + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0000021100b61010_0, 4, 5; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000021100b61330_0, 0; + %jmp T_2.6; +T_2.5 ; + %load/vec4 v0000021100b61330_0; + %pad/u 4; + %cmpi/e 8, 0, 4; + %jmp/0xz T_2.8, 4; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000021100b61330_0, 0; +T_2.8 ; +T_2.6 ; +T_2.3 ; +T_2.1 ; + %jmp T_2; + .thread T_2; + .scope S_00000211009e6550; +T_3 ; + %wait E_0000021100b570c0; + %load/vec4 v0000021100b61010_0; + %dup/vec4; + %pushi/vec4 238, 0, 8; + %cmp/u; + %jmp/1 T_3.0, 6; + %dup/vec4; + %pushi/vec4 237, 0, 8; + %cmp/u; + %jmp/1 T_3.1, 6; + %dup/vec4; + %pushi/vec4 235, 0, 8; + %cmp/u; + %jmp/1 T_3.2, 6; + %dup/vec4; + %pushi/vec4 231, 0, 8; + %cmp/u; + %jmp/1 T_3.3, 6; + %dup/vec4; + %pushi/vec4 222, 0, 8; + %cmp/u; + %jmp/1 T_3.4, 6; + %dup/vec4; + %pushi/vec4 221, 0, 8; + %cmp/u; + %jmp/1 T_3.5, 6; + %dup/vec4; + %pushi/vec4 219, 0, 8; + %cmp/u; + %jmp/1 T_3.6, 6; + %dup/vec4; + %pushi/vec4 215, 0, 8; + %cmp/u; + %jmp/1 T_3.7, 6; + %dup/vec4; + %pushi/vec4 190, 0, 8; + %cmp/u; + %jmp/1 T_3.8, 6; + %dup/vec4; + %pushi/vec4 189, 0, 8; + %cmp/u; + %jmp/1 T_3.9, 6; + %dup/vec4; + %pushi/vec4 187, 0, 8; + %cmp/u; + %jmp/1 T_3.10, 6; + %dup/vec4; + %pushi/vec4 183, 0, 8; + %cmp/u; + %jmp/1 T_3.11, 6; + %dup/vec4; + %pushi/vec4 190, 0, 8; + %cmp/u; + %jmp/1 T_3.12, 6; + %dup/vec4; + %pushi/vec4 189, 0, 8; + %cmp/u; + %jmp/1 T_3.13, 6; + %dup/vec4; + %pushi/vec4 187, 0, 8; + %cmp/u; + %jmp/1 T_3.14, 6; + %dup/vec4; + %pushi/vec4 183, 0, 8; + %cmp/u; + %jmp/1 T_3.15, 6; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %jmp T_3.17; +T_3.0 ; + %pushi/vec4 1, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 1, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.1 ; + %pushi/vec4 2, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 1, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.2 ; + %pushi/vec4 4, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 1, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.3 ; + %pushi/vec4 8, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 1, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.4 ; + %pushi/vec4 16, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 1, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.5 ; + %pushi/vec4 32, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 1, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.6 ; + %pushi/vec4 64, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 1, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.7 ; + %pushi/vec4 128, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 1, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.8 ; + %pushi/vec4 1, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 2, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.9 ; + %pushi/vec4 2, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 2, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.10 ; + %pushi/vec4 4, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 2, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.11 ; + %pushi/vec4 8, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 2, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.12 ; + %pushi/vec4 16, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 2, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.13 ; + %pushi/vec4 32, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 2, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.14 ; + %pushi/vec4 64, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 2, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.15 ; + %pushi/vec4 128, 0, 8; + %assign/vec4 v0000021100b62280_0, 0; + %pushi/vec4 2, 0, 8; + %assign/vec4 v0000021100b61880_0, 0; + %jmp T_3.17; +T_3.17 ; + %pop/vec4 1; + %jmp T_3; + .thread T_3; +# The file index is used to find the file name in the following table. +:file_names 3; + "N/A"; + ""; + "key.v"; diff --git a/led_matrix/key.xdc b/led_matrix/key.xdc new file mode 100644 index 0000000..ce40b2a --- /dev/null +++ b/led_matrix/key.xdc @@ -0,0 +1,54 @@ +create_clock -period 20.000 -name sys_clk [get_ports sys_clk] +set_property PACKAGE_PIN F20 [get_ports o1] +set_property PACKAGE_PIN F19 [get_ports o2] +set_property PACKAGE_PIN B20 [get_ports o3] +set_property PACKAGE_PIN C20 [get_ports o4] +set_property PACKAGE_PIN J16 [get_ports o5] +set_property PACKAGE_PIN K16 [get_ports o6] +set_property PACKAGE_PIN M18 [get_ports o7] +set_property PACKAGE_PIN M17 [get_ports o8] +set_property PACKAGE_PIN N15 [get_ports o9] +set_property PACKAGE_PIN N16 [get_ports o10] +set_property PACKAGE_PIN M14 [get_ports o11] +set_property PACKAGE_PIN M15 [get_ports o12] +set_property PACKAGE_PIN L14 [get_ports o13] +set_property PACKAGE_PIN L15 [get_ports o14] +set_property PACKAGE_PIN L16 [get_ports o15] +set_property PACKAGE_PIN L17 [get_ports o16] +set_property PACKAGE_PIN U18 [get_ports sys_clk] +set_property PACKAGE_PIN J15 [get_ports sys_rst] +set_property IOSTANDARD LVCMOS33 [get_ports o1] +set_property IOSTANDARD LVCMOS33 [get_ports o2] +set_property IOSTANDARD LVCMOS33 [get_ports o3] +set_property IOSTANDARD LVCMOS33 [get_ports o4] +set_property IOSTANDARD LVCMOS33 [get_ports o5] +set_property IOSTANDARD LVCMOS33 [get_ports o6] +set_property IOSTANDARD LVCMOS33 [get_ports o7] +set_property IOSTANDARD LVCMOS33 [get_ports o8] +set_property IOSTANDARD LVCMOS33 [get_ports o9] +set_property IOSTANDARD LVCMOS33 [get_ports o10] +set_property IOSTANDARD LVCMOS33 [get_ports o11] +set_property IOSTANDARD LVCMOS33 [get_ports o13] +set_property IOSTANDARD LVCMOS33 [get_ports o12] +set_property IOSTANDARD LVCMOS33 [get_ports o14] +set_property IOSTANDARD LVCMOS33 [get_ports o15] +set_property IOSTANDARD LVCMOS33 [get_ports o16] +set_property IOSTANDARD LVCMOS33 [get_ports sys_rst] +set_property IOSTANDARD LVCMOS33 [get_ports sys_clk] + +set_property IOSTANDARD LVCMOS33 [get_ports c1] +set_property IOSTANDARD LVCMOS33 [get_ports c2] +set_property IOSTANDARD LVCMOS33 [get_ports c3] +set_property IOSTANDARD LVCMOS33 [get_ports c4] +set_property PACKAGE_PIN A20 [get_ports c1] +set_property PACKAGE_PIN B19 [get_ports c2] +set_property PACKAGE_PIN D19 [get_ports c3] +set_property PACKAGE_PIN D20 [get_ports c4] +set_property IOSTANDARD LVCMOS33 [get_ports r1] +set_property IOSTANDARD LVCMOS33 [get_ports r2] +set_property IOSTANDARD LVCMOS33 [get_ports r3] +set_property IOSTANDARD LVCMOS33 [get_ports r4] +set_property PACKAGE_PIN E19 [get_ports r1] +set_property PACKAGE_PIN E18 [get_ports r2] +set_property PACKAGE_PIN F17 [get_ports r3] +set_property PACKAGE_PIN F16 [get_ports r4]