From 26044eecd5da914810798adb14c747c9ac87c99c Mon Sep 17 00:00:00 2001
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Date: Fri, 17 May 2024 09:09:23 +0800
Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E4=B8=80=E4=BA=9B=E8=AF=B4?=
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---
 ip_1_port_ram/tb_ram.v | 25 ++++++++++++-------------
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/ip_1_port_ram/tb_ram.v b/ip_1_port_ram/tb_ram.v
index 63cb05c..ce0867b 100644
--- a/ip_1_port_ram/tb_ram.v
+++ b/ip_1_port_ram/tb_ram.v
@@ -41,34 +41,33 @@ always @(posedge sys_clk or negedge sys_rst) begin
     end
 end
 
-reg [2:0]ram_data;  // 假想写入的数据, 数据变化范围是0~7, 只有在 ram_rw 是写入的时候进行累加并写入地址内
+
+reg [2:0]ram_addr;  // 地址变化范围 0~7就行了
 always @(posedge sys_clk or negedge sys_rst) begin
     if (!sys_rst) begin
-        ram_data <= 3'b0;
+        ram_addr <= 3'b0;
     end
-    // 如果是写, 并且还没到最大数
-    else if (ram_rw && ram_data < 3'b111) begin
-        ram_data <= ram_data + 3'b1;
+    else if (ram_en && ram_addr < 3'b111) begin
+        ram_addr <= ram_addr + 3'b1;
     end
     else begin
-        ram_data <= 3'b0;
+        ram_addr <= 3'b0;
     end
 end
 
 
-reg [2:0]ram_addr;  // 地址变化范围 0~7就行了
+reg [2:0]ram_data;  // 假想写入的数据, 数据变化范围是0~7, 只有在 ram_rw 是写入的时候进行累加并写入地址内
 always @(posedge sys_clk or negedge sys_rst) begin
     if (!sys_rst) begin
-        ram_addr <= 3'b0;
+        ram_data <= 3'b0;
     end
-    else if (ram_en && ram_addr < 3'b111) begin
-        ram_addr <= ram_addr + 3'b1;
+    // 如果是写, 并且还没到最大数
+    else if (ram_rw && ram_data < 3'b111) begin
+        ram_data <= ram_data + 3'b1;
     end
     else begin
-        ram_addr <= 3'b0;
+        ram_data <= 3'b0;
     end
 end
 
-
-
 endmodule
\ No newline at end of file