From 3816e69714ee2fd80b5c405356efa8ea57199cbf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E9=98=B3=E5=85=89=E5=B0=91=E5=B9=B4?= <849317537@qq.com> Date: Fri, 7 Jun 2024 17:17:37 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BC=98=E5=8C=96=E4=BB=A3=E7=A0=81,=20?= =?UTF-8?q?=E9=98=B2=E6=AD=A2=E5=8F=91=E9=80=81=E8=BF=87=E5=BF=AB=E6=88=96?= =?UTF-8?q?=E8=80=85=E6=99=B6=E6=8C=AF=E5=AF=BC=E8=87=B4=E8=AE=A1=E6=95=B0?= =?UTF-8?q?=E5=99=A8=E8=AF=AF=E5=B7=AE,=20start=5Fen=E5=9C=A8busy=E7=BB=93?= =?UTF-8?q?=E6=9D=9F=E4=B9=8B=E5=89=8D=E5=87=BA=E7=8E=B0=E5=AF=BC=E8=87=B4?= =?UTF-8?q?=E8=AE=A1=E6=95=B0=E5=99=A8=E4=B8=8D=E5=86=8D=E5=B7=A5=E4=BD=9C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- uart/uart_tx.v | 8 +- uart/uart_tx.v.out | 292 ++++++++++++++++++++++++++++++++------------- 2 files changed, 213 insertions(+), 87 deletions(-) diff --git a/uart/uart_tx.v b/uart/uart_tx.v index fe6cb5c..b641fcf 100644 --- a/uart/uart_tx.v +++ b/uart/uart_tx.v @@ -26,7 +26,7 @@ always @(posedge sys_clk or negedge sys_rst) begin temp_tx_data <= tx_data; // 记录外部传过来的并行数据备份 tx_busy <= 'b1; // 拉高 忙信号 end - else if (tx_d_cnt == 'b1001 && baud_cnt == (B_MAX / 16 * 15)-1) begin // 提前结束, 和下次发送拉开时间 + else if (tx_d_cnt == 'b1001 && baud_cnt == B_MAX-1) begin // 发送一个完整的停止位 temp_tx_data <= 'b0; tx_busy <= 0; end @@ -41,6 +41,9 @@ always @(posedge sys_clk or negedge sys_rst) begin if (sys_rst == 1'b0) begin baud_cnt <= 'b0; end + else if (start_en) begin // 又要发送新数据了, 立刻清零重新计数 + baud_cnt <= 'b0; + end // 必须要开始传输数据 else if (tx_busy) begin if (baud_cnt == B_MAX-'b1) begin // 从0开始计数的 0~433 一共计数434次 @@ -60,6 +63,9 @@ always @(posedge sys_clk or negedge sys_rst) begin if (sys_rst == 1'b0) begin tx_d_cnt <= 'b0; end + else if (start_en) begin // 又要发送新数据了, 立刻清零重新计数 + tx_d_cnt <= 'b0; + end // 必须要开始传输数据 else if (tx_busy) begin if (baud_cnt == B_MAX-'b1) begin diff --git a/uart/uart_tx.v.out b/uart/uart_tx.v.out index 7d0c62e..571d151 100755 --- a/uart/uart_tx.v.out +++ b/uart/uart_tx.v.out @@ -7,7 +7,7 @@ :vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi"; :vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi"; :vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi"; -S_0x7fbaa1007ac0 .scope module, "uart_tx" "uart_tx" 2 1; +S_0x7fef0a6042d0 .scope module, "uart_tx" "uart_tx" 2 1; .timescale 0 0; .port_info 0 /INPUT 1 "sys_clk"; .port_info 1 /INPUT 1 "sys_rst"; @@ -15,148 +15,268 @@ S_0x7fbaa1007ac0 .scope module, "uart_tx" "uart_tx" 2 1; .port_info 3 /INPUT 8 "tx_data"; .port_info 4 /OUTPUT 1 "txd"; .port_info 5 /OUTPUT 1 "tx_busy"; -P_0x7fbaa1005e00 .param/l "BPS" 0 2 14, +C4<00000000000000011100001000000000>; -P_0x7fbaa1005e40 .param/l "B_MAX" 1 2 16, +C4<00000000000000000000000110110010>; -P_0x7fbaa1005e80 .param/l "CLK_FREQ" 0 2 13, +C4<00000010111110101111000010000000>; -v0x7fbaa10069a0_0 .var "baud_cnt", 15 0; -o0x7fbaa1432038 .functor BUFZ 1, C4; HiZ drive -v0x7fbaa10179c0_0 .net "start_en", 0 0, o0x7fbaa1432038; 0 drivers -o0x7fbaa1432068 .functor BUFZ 1, C4; HiZ drive -v0x7fbaa1017a60_0 .net "sys_clk", 0 0, o0x7fbaa1432068; 0 drivers -o0x7fbaa1432098 .functor BUFZ 1, C4; HiZ drive -v0x7fbaa1017af0_0 .net "sys_rst", 0 0, o0x7fbaa1432098; 0 drivers -v0x7fbaa1017b90_0 .var "temp_tx_data", 7 0; -v0x7fbaa1017c80_0 .var "tx_busy", 0 0; -v0x7fbaa1017d20_0 .var "tx_d_cnt", 3 0; -o0x7fbaa1432158 .functor BUFZ 8, C4; HiZ drive -v0x7fbaa1017dd0_0 .net "tx_data", 7 0, o0x7fbaa1432158; 0 drivers -v0x7fbaa1017e80_0 .var "txd", 0 0; -E_0x7fbaa1005110/0 .event negedge, v0x7fbaa1017af0_0; -E_0x7fbaa1005110/1 .event posedge, v0x7fbaa1017a60_0; -E_0x7fbaa1005110 .event/or E_0x7fbaa1005110/0, E_0x7fbaa1005110/1; - .scope S_0x7fbaa1007ac0; +P_0x7fef0a604440 .param/l "BPS" 0 2 12, +C4<00000000000000011100001000000000>; +P_0x7fef0a604480 .param/l "B_MAX" 1 2 13, +C4<00000000000000000000000110110010>; +P_0x7fef0a6044c0 .param/l "CLK_FREQ" 0 2 11, +C4<00000010111110101111000010000000>; +v0x7fef0a604760_0 .var "baud_cnt", 15 0; +o0x7fef0a432038 .functor BUFZ 1, C4; HiZ drive +v0x7fef0a515b20_0 .net "start_en", 0 0, o0x7fef0a432038; 0 drivers +o0x7fef0a432068 .functor BUFZ 1, C4; HiZ drive +v0x7fef0a515bd0_0 .net "sys_clk", 0 0, o0x7fef0a432068; 0 drivers +o0x7fef0a432098 .functor BUFZ 1, C4; HiZ drive +v0x7fef0a515c80_0 .net "sys_rst", 0 0, o0x7fef0a432098; 0 drivers +v0x7fef0a515d10_0 .var "temp_tx_data", 7 0; +v0x7fef0a515da0_0 .var "tx_busy", 0 0; +v0x7fef0a515e40_0 .var "tx_d_cnt", 3 0; +o0x7fef0a432158 .functor BUFZ 8, C4; HiZ drive +v0x7fef0a515ef0_0 .net "tx_data", 7 0, o0x7fef0a432158; 0 drivers +v0x7fef0a515fa0_0 .var "txd", 0 0; +E_0x7fef0a604540/0 .event negedge, v0x7fef0a515c80_0; +E_0x7fef0a604540/1 .event posedge, v0x7fef0a515bd0_0; +E_0x7fef0a604540 .event/or E_0x7fef0a604540/0, E_0x7fef0a604540/1; + .scope S_0x7fef0a6042d0; T_0 ; - %wait E_0x7fbaa1005110; - %load/vec4 v0x7fbaa1017af0_0; + %wait E_0x7fef0a604540; + %load/vec4 v0x7fef0a515c80_0; %cmpi/e 0, 0, 1; %jmp/0xz T_0.0, 4; %pushi/vec4 0, 0, 8; - %assign/vec4 v0x7fbaa1017b90_0, 0; + %assign/vec4 v0x7fef0a515d10_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x7fef0a515da0_0, 0; %jmp T_0.1; T_0.0 ; - %load/vec4 v0x7fbaa10179c0_0; + %load/vec4 v0x7fef0a515b20_0; %flag_set/vec4 8; %jmp/0xz T_0.2, 8; - %load/vec4 v0x7fbaa1017dd0_0; - %assign/vec4 v0x7fbaa1017b90_0, 0; + %load/vec4 v0x7fef0a515ef0_0; + %assign/vec4 v0x7fef0a515d10_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x7fef0a515da0_0, 0; + %jmp T_0.3; T_0.2 ; + %load/vec4 v0x7fef0a515e40_0; + %pad/u 32; + %cmpi/e 9, 0, 32; + %flag_get/vec4 4; + %jmp/0 T_0.6, 4; + %load/vec4 v0x7fef0a604760_0; + %pad/u 32; + %pushi/vec4 433, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %and; +T_0.6; + %flag_set/vec4 8; + %jmp/0xz T_0.4, 8; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x7fef0a515d10_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x7fef0a515da0_0, 0; + %jmp T_0.5; +T_0.4 ; + %load/vec4 v0x7fef0a515d10_0; + %assign/vec4 v0x7fef0a515d10_0, 0; + %load/vec4 v0x7fef0a515da0_0; + %assign/vec4 v0x7fef0a515da0_0, 0; +T_0.5 ; +T_0.3 ; T_0.1 ; %jmp T_0; .thread T_0; - .scope S_0x7fbaa1007ac0; + .scope S_0x7fef0a6042d0; T_1 ; - %wait E_0x7fbaa1005110; - %load/vec4 v0x7fbaa1017af0_0; + %wait E_0x7fef0a604540; + %load/vec4 v0x7fef0a515c80_0; %cmpi/e 0, 0, 1; %jmp/0xz T_1.0, 4; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x7fbaa1017c80_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x7fef0a604760_0, 0; %jmp T_1.1; T_1.0 ; - %load/vec4 v0x7fbaa10179c0_0; + %load/vec4 v0x7fef0a515b20_0; %flag_set/vec4 8; %jmp/0xz T_1.2, 8; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x7fbaa1017c80_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x7fef0a604760_0, 0; %jmp T_1.3; T_1.2 ; - %load/vec4 v0x7fbaa1017d20_0; - %pad/u 32; - %cmpi/e 9, 0, 32; - %flag_get/vec4 4; - %jmp/0 T_1.6, 4; - %load/vec4 v0x7fbaa10069a0_0; - %pad/u 32; - %pushi/vec4 404, 0, 32; - %cmp/e; - %flag_get/vec4 4; - %and; -T_1.6; + %load/vec4 v0x7fef0a515da0_0; %flag_set/vec4 8; %jmp/0xz T_1.4, 8; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x7fbaa1017c80_0, 0; + %load/vec4 v0x7fef0a604760_0; + %pad/u 32; + %cmpi/e 433, 0, 32; + %jmp/0xz T_1.6, 4; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x7fef0a604760_0, 0; + %jmp T_1.7; +T_1.6 ; + %load/vec4 v0x7fef0a604760_0; + %addi 1, 0, 16; + %assign/vec4 v0x7fef0a604760_0, 0; +T_1.7 ; %jmp T_1.5; T_1.4 ; - %load/vec4 v0x7fbaa1017c80_0; - %assign/vec4 v0x7fbaa1017c80_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x7fef0a604760_0, 0; T_1.5 ; T_1.3 ; T_1.1 ; %jmp T_1; .thread T_1; - .scope S_0x7fbaa1007ac0; + .scope S_0x7fef0a6042d0; T_2 ; - %wait E_0x7fbaa1005110; - %load/vec4 v0x7fbaa1017af0_0; + %wait E_0x7fef0a604540; + %load/vec4 v0x7fef0a515c80_0; %cmpi/e 0, 0, 1; %jmp/0xz T_2.0, 4; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x7fbaa10069a0_0, 0; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x7fef0a515e40_0, 0; %jmp T_2.1; T_2.0 ; - %load/vec4 v0x7fbaa1017c80_0; + %load/vec4 v0x7fef0a515b20_0; %flag_set/vec4 8; %jmp/0xz T_2.2, 8; - %load/vec4 v0x7fbaa10069a0_0; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x7fef0a515e40_0, 0; + %jmp T_2.3; +T_2.2 ; + %load/vec4 v0x7fef0a515da0_0; + %flag_set/vec4 8; + %jmp/0xz T_2.4, 8; + %load/vec4 v0x7fef0a604760_0; %pad/u 32; %cmpi/e 433, 0, 32; - %jmp/0xz T_2.4, 4; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x7fbaa10069a0_0, 0; + %jmp/0xz T_2.6, 4; + %load/vec4 v0x7fef0a515e40_0; + %addi 1, 0, 4; + %assign/vec4 v0x7fef0a515e40_0, 0; + %jmp T_2.7; +T_2.6 ; + %load/vec4 v0x7fef0a515e40_0; + %assign/vec4 v0x7fef0a515e40_0, 0; +T_2.7 ; %jmp T_2.5; T_2.4 ; - %load/vec4 v0x7fbaa10069a0_0; - %addi 1, 0, 16; - %assign/vec4 v0x7fbaa10069a0_0, 0; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x7fef0a515e40_0, 0; T_2.5 ; - %jmp T_2.3; -T_2.2 ; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x7fbaa10069a0_0, 0; T_2.3 ; T_2.1 ; %jmp T_2; .thread T_2; - .scope S_0x7fbaa1007ac0; + .scope S_0x7fef0a6042d0; T_3 ; - %wait E_0x7fbaa1005110; - %load/vec4 v0x7fbaa1017af0_0; + %wait E_0x7fef0a604540; + %load/vec4 v0x7fef0a515c80_0; %cmpi/e 0, 0, 1; %jmp/0xz T_3.0, 4; - %pushi/vec4 0, 0, 4; - %assign/vec4 v0x7fbaa1017d20_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x7fef0a515fa0_0, 0; %jmp T_3.1; T_3.0 ; - %load/vec4 v0x7fbaa1017c80_0; + %load/vec4 v0x7fef0a515da0_0; %flag_set/vec4 8; %jmp/0xz T_3.2, 8; - %load/vec4 v0x7fbaa10069a0_0; - %pad/u 32; - %cmpi/e 433, 0, 32; - %jmp/0xz T_3.4, 4; - %load/vec4 v0x7fbaa1017d20_0; - %addi 1, 0, 4; - %assign/vec4 v0x7fbaa1017d20_0, 0; - %jmp T_3.5; + %load/vec4 v0x7fef0a515e40_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_3.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_3.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_3.6, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_3.7, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_3.8, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_3.9, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_3.10, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_3.11, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_3.12, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_3.13, 6; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x7fef0a515fa0_0, 0; + %jmp T_3.15; T_3.4 ; - %load/vec4 v0x7fbaa1017d20_0; - %assign/vec4 v0x7fbaa1017d20_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x7fef0a515fa0_0, 0; + %jmp T_3.15; T_3.5 ; + %load/vec4 v0x7fef0a515d10_0; + %parti/s 1, 0, 2; + %assign/vec4 v0x7fef0a515fa0_0, 0; + %jmp T_3.15; +T_3.6 ; + %load/vec4 v0x7fef0a515d10_0; + %parti/s 1, 1, 2; + %assign/vec4 v0x7fef0a515fa0_0, 0; + %jmp T_3.15; +T_3.7 ; + %load/vec4 v0x7fef0a515d10_0; + %parti/s 1, 2, 3; + %assign/vec4 v0x7fef0a515fa0_0, 0; + %jmp T_3.15; +T_3.8 ; + %load/vec4 v0x7fef0a515d10_0; + %parti/s 1, 3, 3; + %assign/vec4 v0x7fef0a515fa0_0, 0; + %jmp T_3.15; +T_3.9 ; + %load/vec4 v0x7fef0a515d10_0; + %parti/s 1, 4, 4; + %assign/vec4 v0x7fef0a515fa0_0, 0; + %jmp T_3.15; +T_3.10 ; + %load/vec4 v0x7fef0a515d10_0; + %parti/s 1, 5, 4; + %assign/vec4 v0x7fef0a515fa0_0, 0; + %jmp T_3.15; +T_3.11 ; + %load/vec4 v0x7fef0a515d10_0; + %parti/s 1, 6, 4; + %assign/vec4 v0x7fef0a515fa0_0, 0; + %jmp T_3.15; +T_3.12 ; + %load/vec4 v0x7fef0a515d10_0; + %parti/s 1, 7, 4; + %assign/vec4 v0x7fef0a515fa0_0, 0; + %jmp T_3.15; +T_3.13 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x7fef0a515fa0_0, 0; + %jmp T_3.15; +T_3.15 ; + %pop/vec4 1; %jmp T_3.3; T_3.2 ; - %pushi/vec4 0, 0, 4; - %assign/vec4 v0x7fbaa1017d20_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x7fef0a515fa0_0, 0; T_3.3 ; T_3.1 ; %jmp T_3;