diff --git a/ip_1_port_ram/tb_ram.v b/ip_1_port_ram/tb_ram.v new file mode 100644 index 0000000..00481fa --- /dev/null +++ b/ip_1_port_ram/tb_ram.v @@ -0,0 +1,75 @@ +`timescale 1ns/1ns +module tb_ram(); + +reg sys_clk; +reg sys_rst; +always #10 sys_clk = ~sys_clk; + + +initial begin + sys_clk <= 1'b0; + sys_rst <= 1'b0; + #50 + sys_rst <= 1'b1; +end + +reg ram_en; +always @(posedge sys_clk or negedge sys_rst) begin + if (!sys_rst) begin + ram_en <= 1'b0; + end + // 只有在复位之后, 才允许启动ram + else begin + ram_en <= 1'b1; + end +end + + +reg [7:0]counter; // 计数到15 清零, 变化范围 0~15 +wire ram_rw; +assign ram_rw = ram_en && (counter <= 8'b111); // 计数器 分成读写各占一半时间, 0~7的时候高电平进行写, 8~15低电平进行读取 +always @(posedge sys_clk or negedge sys_rst) begin + if (!sys_rst) begin + counter <= 8'b0; + end + // 没有启用ram禁止计数 + else if (ram_en == 1'b0 || counter == 8'b1111) begin + counter <= 8'b0; + end + else begin + counter <= counter + 8'b1; + end +end + +reg [2:0]ram_data; // 假想写入的数据, 数据变化范围是0~7, 只有在 ram_rw 是写入的时候进行累加并写入地址内 +always @(posedge sys_clk or negedge sys_rst) begin + if (!sys_rst) begin + ram_data <= 3'b0; + end + // 如果是写, 并且还没到最大数 + else if (ram_rw && ram_data < 3'b111) begin + ram_data <= ram_data + 3'b1; + end + else begin + ram_data <= 3'b0; + end +end + + +reg [2:0]ram_addr; // 地址变化范围 0~7就行了 +always @(posedge sys_clk or negedge sys_rst) begin + if (!sys_rst) begin + ram_addr <= 3'b0; + end + // 没有启用ram禁止计数 + else if (ram_en == 1'b0 && ram_addr == 3'b111) begin + ram_addr <= 3'b0; + end + else begin + ram_addr <= ram_addr + 3'b1; + end +end + + + +endmodule \ No newline at end of file diff --git a/ip_1_port_ram/tb_ram.v.out b/ip_1_port_ram/tb_ram.v.out new file mode 100755 index 0000000..754c785 --- /dev/null +++ b/ip_1_port_ram/tb_ram.v.out @@ -0,0 +1,153 @@ +#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp +:ivl_version "12.0 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 9; +:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi"; +:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi"; +:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi"; +S_0x7fe52f706430 .scope module, "tb_ram" "tb_ram" 2 2; + .timescale -9 -9; +L_0x7fe52f716d40 .functor AND 1, v0x7fe52f716950_0, L_0x7fe52f716c60, C4<1>, C4<1>; +L_0x7fe530163008 .functor BUFT 1, C4<00000111>, C4<0>, C4<0>, C4<0>; +v0x7fe52f7065b0_0 .net/2u *"_ivl_0", 7 0, L_0x7fe530163008; 1 drivers +v0x7fe52f716670_0 .net *"_ivl_2", 0 0, L_0x7fe52f716c60; 1 drivers +v0x7fe52f716710_0 .var "counter", 7 0; +v0x7fe52f7167b0_0 .var "ram_addr", 2 0; +v0x7fe52f716860_0 .var "ram_data", 2 0; +v0x7fe52f716950_0 .var "ram_en", 0 0; +v0x7fe52f7169f0_0 .net "ram_rw", 0 0, L_0x7fe52f716d40; 1 drivers +v0x7fe52f716a90_0 .var "sys_clk", 0 0; +v0x7fe52f716b30_0 .var "sys_rst", 0 0; +E_0x7fe52f706320/0 .event negedge, v0x7fe52f716b30_0; +E_0x7fe52f706320/1 .event posedge, v0x7fe52f716a90_0; +E_0x7fe52f706320 .event/or E_0x7fe52f706320/0, E_0x7fe52f706320/1; +L_0x7fe52f716c60 .cmp/ge 8, L_0x7fe530163008, v0x7fe52f716710_0; + .scope S_0x7fe52f706430; +T_0 ; + %delay 10, 0; + %load/vec4 v0x7fe52f716a90_0; + %inv; + %store/vec4 v0x7fe52f716a90_0, 0, 1; + %jmp T_0; + .thread T_0; + .scope S_0x7fe52f706430; +T_1 ; + %wait E_0x7fe52f706320; + %load/vec4 v0x7fe52f716b30_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_1.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x7fe52f716950_0, 0; + %jmp T_1.1; +T_1.0 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x7fe52f716950_0, 0; +T_1.1 ; + %jmp T_1; + .thread T_1; + .scope S_0x7fe52f706430; +T_2 ; + %wait E_0x7fe52f706320; + %load/vec4 v0x7fe52f716b30_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x7fe52f716710_0, 0; + %jmp T_2.1; +T_2.0 ; + %load/vec4 v0x7fe52f716950_0; + %cmpi/e 0, 0, 1; + %jmp/1 T_2.4, 4; + %flag_mov 8, 4; + %load/vec4 v0x7fe52f716710_0; + %cmpi/e 15, 0, 8; + %flag_or 4, 8; +T_2.4; + %jmp/0xz T_2.2, 4; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x7fe52f716710_0, 0; + %jmp T_2.3; +T_2.2 ; + %load/vec4 v0x7fe52f716710_0; + %addi 1, 0, 8; + %assign/vec4 v0x7fe52f716710_0, 0; +T_2.3 ; +T_2.1 ; + %jmp T_2; + .thread T_2; + .scope S_0x7fe52f706430; +T_3 ; + %wait E_0x7fe52f706320; + %load/vec4 v0x7fe52f716b30_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_3.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x7fe52f716860_0, 0; + %jmp T_3.1; +T_3.0 ; + %load/vec4 v0x7fe52f7169f0_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_3.4, 9; + %load/vec4 v0x7fe52f716860_0; + %cmpi/u 7, 0, 3; + %flag_get/vec4 5; + %and; +T_3.4; + %flag_set/vec4 8; + %jmp/0xz T_3.2, 8; + %load/vec4 v0x7fe52f716860_0; + %addi 1, 0, 3; + %assign/vec4 v0x7fe52f716860_0, 0; + %jmp T_3.3; +T_3.2 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x7fe52f716860_0, 0; +T_3.3 ; +T_3.1 ; + %jmp T_3; + .thread T_3; + .scope S_0x7fe52f706430; +T_4 ; + %wait E_0x7fe52f706320; + %load/vec4 v0x7fe52f716b30_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_4.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x7fe52f7167b0_0, 0; + %jmp T_4.1; +T_4.0 ; + %load/vec4 v0x7fe52f716950_0; + %cmpi/e 0, 0, 1; + %flag_get/vec4 4; + %jmp/0 T_4.4, 4; + %load/vec4 v0x7fe52f7167b0_0; + %pushi/vec4 7, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; +T_4.4; + %flag_set/vec4 8; + %jmp/0xz T_4.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x7fe52f7167b0_0, 0; + %jmp T_4.3; +T_4.2 ; + %load/vec4 v0x7fe52f7167b0_0; + %addi 1, 0, 3; + %assign/vec4 v0x7fe52f7167b0_0, 0; +T_4.3 ; +T_4.1 ; + %jmp T_4; + .thread T_4; +# The file index is used to find the file name in the following table. +:file_names 3; + "N/A"; + ""; + "tb_ram.v";