简单优化

main
阳光少年 8 months ago
parent 77caedf906
commit 3eb9fc25f7

@ -47,8 +47,7 @@ reg [7:0]x;
reg [7:0]y;
always @(posedge sys_clk or negedge sys_rst) begin
if (sys_rst == 1'b0) begin
k_1 <= 1'b0;
k_2 <= 1'b0;
{k_2, k_1} <= 2'b11;
x <= 8'b00000000;
y <= 8'b11111111; //
end

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