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verilog_stu
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修改STATUS的问题

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阳光少年 8 months ago
parent 1d1c80e051
commit 5a6515135e
1 changed files with 6 additions and 75 deletions
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81
led_matrix/key.v
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@ -3,7 +3,7 @@ module key_1(
input wire sys_rst, //J15
// d20,d19,b19,a20
output reg c4, c3, c2, c1,
// f16.f17,e18,e19
// f16,f17,e18,e19
output reg r4, r3, r2, r1,
// f20 f19 b20 c20 j16 k16 m18 m17 l17 l16 l15 l14 m15 m14 n16 n15
@ -13,10 +13,10 @@ module key_1(
);
reg [7:0] KEY_CODE;
parameter GET_START = 4'b0010;
parameter GET_ROW = 4'b0010;
parameter GET_COL = 4'b0100;
parameter GET_END = 4'b1000;
parameter GET_START = 4'b0001 << 0;
parameter GET_ROW = 4'b0001 << 1;
parameter GET_COL = 4'b0001 << 2;
parameter GET_END = 4'b0001 << 3;
reg STATUS = 4'b0000;
@ -65,78 +65,9 @@ always @(posedge sys_clk or negedge sys_rst) begin
x <= 8'b0000_0000;
end
else begin
x <= KEY_CODE
end
case (KEY_CODE)
8'b1110_1110: begin
x <= 8'b0000_0001;
y <= 8'b0000_0001;
end
8'b1110_1101: begin
x <= 8'b0000_0010;
y <= 8'b0000_0001;
end
8'b1110_1011: begin
x <= 8'b0000_0100;
y <= 8'b0000_0001;
end
8'b1110_0111: begin
x <= 8'b0000_1000;
y <= 8'b0000_0001;
end
8'b1101_1110: begin
x <= 8'b0001_0000;
y <= 8'b0000_0001;
end
8'b1101_1101: begin
x <= 8'b0010_0000;
y <= 8'b0000_0001;
end
8'b1101_1011: begin
x <= 8'b0100_0000;
y <= 8'b0000_0001;
end
8'b1101_0111: begin
x <= 8'b1000_0000;
y <= 8'b0000_0001;
end
8'b1011_1110: begin
x <= 8'b0000_0001;
y <= 8'b0000_0010;
end
8'b1011_1101: begin
x <= 8'b0000_0010;
y <= 8'b0000_0010;
end
8'b1011_1011: begin
x <= 8'b0000_0100;
y <= 8'b0000_0010;
end
8'b1011_0111: begin
x <= 8'b0000_1000;
y <= 8'b0000_0010;
end
8'b1011_1110: begin
x <= 8'b0001_0000;
y <= 8'b0000_0010;
end
8'b1011_1101: begin
x <= 8'b0010_0000;
y <= 8'b0000_0010;
end
8'b1011_1011: begin
x <= 8'b0100_0000;
y <= 8'b0000_0010;
end
8'b1011_0111: begin
x <= 8'b1000_0000;
y <= 8'b0000_0010;
end
default: x <= 8'b0000_1000;
endcase
end

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