From 6e2459ac6dc75d6477c3c0f2cbd87bae468d35ad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E9=98=B3=E5=85=89=E5=B0=91=E5=B9=B4?= <849317537@qq.com> Date: Fri, 10 May 2024 21:13:34 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BB=93=E5=BA=93=E6=96=87=E4=BB=B6=E6=95=B4?= =?UTF-8?q?=E7=90=86?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- led.v.out | 71 -------------------------------------------- led/led.v | 10 +++++++ led/led.v.out | 30 +++++++++++++++++++ led.v => led/led_1.v | 0 led/led_1.v.out | 71 ++++++++++++++++++++++++++++++++++++++++++++ led/tb_led.v | 26 ++++++++++++++++ 6 files changed, 137 insertions(+), 71 deletions(-) delete mode 100755 led.v.out create mode 100644 led/led.v create mode 100644 led/led.v.out rename led.v => led/led_1.v (100%) create mode 100644 led/led_1.v.out create mode 100644 led/tb_led.v diff --git a/led.v.out b/led.v.out deleted file mode 100755 index 598f0ae..0000000 --- a/led.v.out +++ /dev/null @@ -1,71 +0,0 @@ -#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp -:ivl_version "12.0 (stable)"; -:ivl_delay_selection "TYPICAL"; -:vpi_time_precision + 0; -:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi"; -:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi"; -:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi"; -:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi"; -:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi"; -S_0x7f920c80a740 .scope module, "led" "led" 2 1; - .timescale 0 0; - .port_info 0 /INPUT 1 "key"; - .port_info 1 /OUTPUT 1 "led"; -o0x7f920c9322d8 .functor BUFZ 1, C4; HiZ drive -L_0x7f920c81aae0 .functor BUFZ 1, o0x7f920c9322d8, C4<0>, C4<0>, C4<0>; -L_0x7f920c9630e0 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>; -v0x7f920c805670_0 .net *"_ivl_17", 1 0, L_0x7f920c9630e0; 1 drivers -L_0x7f920c963128 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>; -v0x7f920c81a550_0 .net *"_ivl_21", 1 0, L_0x7f920c963128; 1 drivers -v0x7f920c81a5f0_0 .net *"_ivl_25", 1 0, L_0x7f920ca06e10; 1 drivers -v0x7f920c81a6a0_0 .net *"_ivl_27", 0 0, L_0x7f920ca06f50; 1 drivers -v0x7f920c81a750_0 .net *"_ivl_29", 0 0, L_0x7f920ca06ff0; 1 drivers -v0x7f920c81a840_0 .net *"_ivl_3", 0 0, L_0x7f920c81aae0; 1 drivers -L_0x7f920c963170 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>; -v0x7f920c81a8f0_0 .net *"_ivl_35", 1 0, L_0x7f920c963170; 1 drivers -L_0x7f920c9631b8 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>; -v0x7f920c81a9a0_0 .net *"_ivl_39", 1 0, L_0x7f920c9631b8; 1 drivers -v0x7f920c81aa50_0 .net *"_ivl_43", 1 0, L_0x7f920ca07090; 1 drivers -o0x7f920c9321b8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x7f920c81ab60_0 name=_ivl_49 -v0x7f920c81ac10_0 .net *"_ivl_7", 0 0, L_0x7f920c81b460; 1 drivers -L_0x7f920c963050 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; -v0x7f920c81acc0_0 .net "a", 0 0, L_0x7f920c963050; 1 drivers -L_0x7f920c963098 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; -v0x7f920c81ad60_0 .net "b", 0 0, L_0x7f920c963098; 1 drivers -L_0x7f920c963008 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -v0x7f920c81ae00_0 .net "c", 0 0, L_0x7f920c963008; 1 drivers -v0x7f920c81aea0_0 .net "d", 0 0, L_0x7f920ca06d70; 1 drivers -v0x7f920c81af40_0 .net "key", 0 0, o0x7f920c9322d8; 0 drivers -v0x7f920c81afe0_0 .var "led", 0 0; -v0x7f920c81b170_0 .net "ret", 1 0, L_0x7f920ca06eb0; 1 drivers -v0x7f920c81b200_0 .net "s", 0 0, L_0x7f920ca06cd0; 1 drivers -v0x7f920c81b290_0 .var "v_reg", 5 0; -v0x7f920c81b340_0 .net "v_wire", 5 0, L_0x7f920ca07130; 1 drivers -E_0x7f920c80a8b0 .event anyedge, v0x7f920c81af40_0; -L_0x7f920c81b460 .part v0x7f920c81b290_0, 1, 1; -L_0x7f920ca06cd0 .part L_0x7f920ca06e10, 1, 1; -L_0x7f920ca06d70 .part L_0x7f920ca06e10, 0, 1; -L_0x7f920ca06e10 .arith/sum 2, L_0x7f920c9630e0, L_0x7f920c963128; -L_0x7f920ca06eb0 .concat8 [ 1 1 0 0], L_0x7f920ca06ff0, L_0x7f920ca06f50; -L_0x7f920ca06f50 .part L_0x7f920ca07090, 1, 1; -L_0x7f920ca06ff0 .part L_0x7f920ca07090, 0, 1; -L_0x7f920ca07090 .arith/sum 2, L_0x7f920c963170, L_0x7f920c9631b8; -L_0x7f920ca07130 .concat [ 1 1 4 0], L_0x7f920c81aae0, L_0x7f920c81b460, o0x7f920c9321b8; - .scope S_0x7f920c80a740; -T_0 ; - %wait E_0x7f920c80a8b0; - %load/vec4 v0x7f920c81af40_0; - %nor/r; - %store/vec4 v0x7f920c81afe0_0, 0, 1; - %load/vec4 v0x7f920c81af40_0; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %store/vec4 v0x7f920c81b290_0, 4, 1; - %jmp T_0; - .thread T_0, $push; -# The file index is used to find the file name in the following table. -:file_names 3; - "N/A"; - ""; - "led.v"; diff --git a/led/led.v b/led/led.v new file mode 100644 index 0000000..41769b0 --- /dev/null +++ b/led/led.v @@ -0,0 +1,10 @@ +module led ( + input wire key, + output reg led +); + +always @(*) begin + led = !key; +end + +endmodule \ No newline at end of file diff --git a/led/led.v.out b/led/led.v.out new file mode 100644 index 0000000..303720e --- /dev/null +++ b/led/led.v.out @@ -0,0 +1,30 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "C:\iverilog\lib\ivl\system.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "C:\iverilog\lib\ivl\va_math.vpi"; +S_000001ec955469d0 .scope module, "led" "led" 2 1; + .timescale 0 0; + .port_info 0 /INPUT 1 "key"; + .port_info 1 /OUTPUT 1 "led"; +o000001ec95426728 .functor BUFZ 1, C4; HiZ drive +v000001ec95546f00_0 .net "key", 0 0, o000001ec95426728; 0 drivers +v000001ec95547190_0 .var "led", 0 0; +E_000001ec95424d90 .event anyedge, v000001ec95546f00_0; + .scope S_000001ec955469d0; +T_0 ; + %wait E_000001ec95424d90; + %load/vec4 v000001ec95546f00_0; + %nor/r; + %store/vec4 v000001ec95547190_0, 0, 1; + %jmp T_0; + .thread T_0, $push; +# The file index is used to find the file name in the following table. +:file_names 3; + "N/A"; + ""; + "led.v"; diff --git a/led.v b/led/led_1.v similarity index 100% rename from led.v rename to led/led_1.v diff --git a/led/led_1.v.out b/led/led_1.v.out new file mode 100644 index 0000000..3b8d6a7 --- /dev/null +++ b/led/led_1.v.out @@ -0,0 +1,71 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "C:\iverilog\lib\ivl\system.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "C:\iverilog\lib\ivl\va_math.vpi"; +S_00000129b79d9e80 .scope module, "led" "led" 2 1; + .timescale 0 0; + .port_info 0 /INPUT 1 "key"; + .port_info 1 /OUTPUT 1 "led"; +o00000129b78b72a8 .functor BUFZ 1, C4; HiZ drive +L_00000129b78a4e80 .functor BUFZ 1, o00000129b78b72a8, C4<0>, C4<0>, C4<0>; +L_00000129b78ff920 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>; +v00000129b78a7900_0 .net *"_ivl_17", 1 0, L_00000129b78ff920; 1 drivers +L_00000129b78ff968 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>; +v00000129b78a7720_0 .net *"_ivl_21", 1 0, L_00000129b78ff968; 1 drivers +v00000129b78a7b80_0 .net *"_ivl_25", 1 0, L_00000129b78b1f80; 1 drivers +v00000129b78a7680_0 .net *"_ivl_27", 0 0, L_00000129b78b0860; 1 drivers +v00000129b78a79a0_0 .net *"_ivl_29", 0 0, L_00000129b78b1120; 1 drivers +v00000129b78a7e00_0 .net *"_ivl_3", 0 0, L_00000129b78a4e80; 1 drivers +L_00000129b78ff9b0 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>; +v00000129b78a7a40_0 .net *"_ivl_35", 1 0, L_00000129b78ff9b0; 1 drivers +L_00000129b78ff9f8 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>; +v00000129b78a77c0_0 .net *"_ivl_39", 1 0, L_00000129b78ff9f8; 1 drivers +v00000129b78a7ae0_0 .net *"_ivl_43", 1 0, L_00000129b78b0fe0; 1 drivers +o00000129b78b7188 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v00000129b78a7860_0 name=_ivl_49 +v00000129b78a8440_0 .net *"_ivl_7", 0 0, L_00000129b78a7fe0; 1 drivers +L_00000129b78ff890 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v00000129b78a7cc0_0 .net "a", 0 0, L_00000129b78ff890; 1 drivers +L_00000129b78ff8d8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v00000129b78a7d60_0 .net "b", 0 0, L_00000129b78ff8d8; 1 drivers +L_00000129b78ff848 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v00000129b78a81c0_0 .net "c", 0 0, L_00000129b78ff848; 1 drivers +v00000129b78a7ea0_0 .net "d", 0 0, L_00000129b78a75e0; 1 drivers +v00000129b78a7540_0 .net "key", 0 0, o00000129b78b72a8; 0 drivers +v00000129b78a7f40_0 .var "led", 0 0; +v00000129b78a8120_0 .net "ret", 1 0, L_00000129b78b1620; 1 drivers +v00000129b78a8080_0 .net "s", 0 0, L_00000129b78a83a0; 1 drivers +v00000129b78a8260_0 .var "v_reg", 5 0; +v00000129b78a8300_0 .net "v_wire", 5 0, L_00000129b78b1da0; 1 drivers +E_00000129b79dc2b0 .event anyedge, v00000129b78a7540_0; +L_00000129b78a7fe0 .part v00000129b78a8260_0, 1, 1; +L_00000129b78a83a0 .part L_00000129b78b1f80, 1, 1; +L_00000129b78a75e0 .part L_00000129b78b1f80, 0, 1; +L_00000129b78b1f80 .arith/sum 2, L_00000129b78ff920, L_00000129b78ff968; +L_00000129b78b1620 .concat8 [ 1 1 0 0], L_00000129b78b1120, L_00000129b78b0860; +L_00000129b78b0860 .part L_00000129b78b0fe0, 1, 1; +L_00000129b78b1120 .part L_00000129b78b0fe0, 0, 1; +L_00000129b78b0fe0 .arith/sum 2, L_00000129b78ff9b0, L_00000129b78ff9f8; +L_00000129b78b1da0 .concat [ 1 1 4 0], L_00000129b78a4e80, L_00000129b78a7fe0, o00000129b78b7188; + .scope S_00000129b79d9e80; +T_0 ; + %wait E_00000129b79dc2b0; + %load/vec4 v00000129b78a7540_0; + %nor/r; + %store/vec4 v00000129b78a7f40_0, 0, 1; + %load/vec4 v00000129b78a7540_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4 v00000129b78a8260_0, 4, 1; + %jmp T_0; + .thread T_0, $push; +# The file index is used to find the file name in the following table. +:file_names 3; + "N/A"; + ""; + "led_1.v"; diff --git a/led/tb_led.v b/led/tb_led.v new file mode 100644 index 0000000..f62a2e3 --- /dev/null +++ b/led/tb_led.v @@ -0,0 +1,26 @@ +module td_led (); +`timescale 1ns/1ns // 睡眠的 单位/精度 + +reg td_key; // 定义内内部的信号 设置为寄存器类型(按键是在 initial 语句中赋值, 以使用寄存器类型) +wire td_led; // 定义内部的输出信号, 使用 wire 类型 + +// 信号初始化的设置 +initial begin + td_key <= 1'b1; // 不阻塞的设置内部初始值 + + #200; // 阻塞 200ns + td_key <= 1'b0; + + #500; + td_key <= 1'b1; + + #1000; + td_key <= 1'b0; +end + +// 例化 +led u_led( + .key (td_key), + .led (td_led) +); +endmodule \ No newline at end of file