From 720eabcfe420c70540694944511aa81b320b5046 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E9=98=B3=E5=85=89=E5=B0=91=E5=B9=B4?= <849317537@qq.com>
Date: Tue, 14 May 2024 11:23:41 +0800
Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E5=8D=95=E8=AF=8D=E6=8B=BC?=
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---
 digital_tube/tb_dt.v     | 2 +-
 digital_tube/test_dt.xdc | 2 +-
 led_matrix/test.v        | 1 -
 led_matrix/test_lm.xdc   | 2 +-
 4 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/digital_tube/tb_dt.v b/digital_tube/tb_dt.v
index 0e0ca20..a9ead74 100644
--- a/digital_tube/tb_dt.v
+++ b/digital_tube/tb_dt.v
@@ -2,7 +2,7 @@
 module tb_dt();
 
 // 我们如果上板验证, 需要再 .xdc文件中, 添加时钟约束
-// create_clock -period 20.000 -name sys_clk [get_posts sys_clk]  
+// create_clock -period 20.000 -name sys_clk [get_ports sys_clk]  
 // 创建一个时钟, 周期是20纳秒, 对应的端口是系统时钟
 
 reg sys_clk;
diff --git a/digital_tube/test_dt.xdc b/digital_tube/test_dt.xdc
index 1bcec74..6c5b674 100644
--- a/digital_tube/test_dt.xdc
+++ b/digital_tube/test_dt.xdc
@@ -1,4 +1,4 @@
-create_clock -period 20.000 -name sys_clk [get_posts sys_clk]  
+create_clock -period 20.000 -name sys_clk [get_ports sys_clk]  
 set_property IOSTANDARD LVCMOS33 [get_ports A]
 set_property IOSTANDARD LVCMOS33 [get_ports sys_rst]
 set_property IOSTANDARD LVCMOS33 [get_ports sys_clk]
diff --git a/led_matrix/test.v b/led_matrix/test.v
index e555796..7498518 100644
--- a/led_matrix/test.v
+++ b/led_matrix/test.v
@@ -32,7 +32,6 @@ always @(posedge sys_clk or negedge sys_rst) begin
     end
     else if (CNT == (25'd25000000 - 25'd1)) begin
         // 推进状态, 选择一行x
-        // x <= 8'b1010_1100;
         x <= show_data[(Y_IDX * 8)+:8];
     end
     else begin
diff --git a/led_matrix/test_lm.xdc b/led_matrix/test_lm.xdc
index a54479b..f80f8b7 100644
--- a/led_matrix/test_lm.xdc
+++ b/led_matrix/test_lm.xdc
@@ -1,4 +1,4 @@
-create_clock -period 20.000 -name sys_clk [get_posts sys_clk]  
+create_clock -period 20.000 -name sys_clk [get_ports sys_clk]  
 set_property PACKAGE_PIN F20 [get_ports o1]
 set_property PACKAGE_PIN F19 [get_ports o2]
 set_property PACKAGE_PIN B20 [get_ports o3]