From 8bc2134ec86699976ec7a168480ed334bcafbea6 Mon Sep 17 00:00:00 2001
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Date: Tue, 4 Jun 2024 18:22:12 +0800
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---
 ip_1_port_ram/ram.v | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/ip_1_port_ram/ram.v b/ip_1_port_ram/ram.v
index d8c7751..454c766 100644
--- a/ip_1_port_ram/ram.v
+++ b/ip_1_port_ram/ram.v
@@ -9,9 +9,7 @@ module ram(
 );
 
 
-
-
-(*mark_debug="true"*)reg [2:0]ram_addr;  // 数据深度为8, 地址变化范围 0~7就行了
+(*mark_debug="true"*)reg [2:0]ram_addr;  // 数据深度为8, 地址变化范围 0~7就行了, 每个时钟周期加1, 直到溢出从0开始
 (*mark_debug="true"*)reg [2:0]in_ram_data;  // 数据宽度为3, 假想写入的数据, 数据变化范围是0~7, 只有在 ram_rw 是写入的时候进行累加并写入地址内
 (*mark_debug="true"*)wire [2:0]out_ram_data;
 
@@ -27,8 +25,8 @@ always @(posedge sys_clk or negedge sys_rst) begin
 end
 
 
-(*mark_debug="true"*)reg [7:0]counter;  // 计数到15 清零, 变化范围 0~15
-wire ram_rw;
+(*mark_debug="true"*)reg [7:0]counter;  // 计数到15 清零, 变化范围 0~15, 0~7是写, 8~15是读
+wire ram_rw;  // 是否可写/可读
 (*mark_debug="true"*)assign ram_rw = ram_en && (counter <= 8'b111);  // 计数器 分成读写各占一半时间
 always @(posedge sys_clk or negedge sys_rst) begin
     if (!sys_rst) begin