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添加一些说明

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阳光少年 8 months ago
parent 1aad27244b
commit 9a0989edfb
5 changed files with 108 additions and 58 deletions
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9
led/led_1.v
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@ -3,8 +3,13 @@ module led( // 该括号内对 io口 以及类型 进行说明
output reg led // 因为需要再always中改变状态, 需要设置为寄存器型
);
reg [5:0]v_reg; // 定义一个 线类型, 宽度为 6bit
wire [5:0]v_wire; // 定义一个 寄存器类型, 宽度为 6bit
parameter WIDTH = 5; // 定义一个内部常量, 可以供模块式用, 当然你这个变量可以在外部被修改, 编译的时候使用
wire [WIDTH:0] tmp1, tmp2; // 定义两个 线类型信号, 宽度为 常量 WIDTH
reg [WIDTH:0]v_reg; // 定义一个 寄存器类型, 宽度为 6bit 寄存器类型在下一次触发机制到来之前, 保留原值
wire [WIDTH:0]v_wire; // 定义一个 线类型, 宽度为 6bit
always @(*) begin // * 表示内部的任何变量发生变化的时候, 就会并行执行该 block
// 该块 没有带时钟信号, 虽然内部产生的信号定义还是 reg型的, 但是他并没有产生时序逻辑, 还是组合逻辑, 只有带时钟信号之后, 才会使用真正的存储单元/寄存器

111
led/led_1.v.out
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@ -1,67 +1,68 @@
#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp
:ivl_version "12.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_00000129b79d9e80 .scope module, "led" "led" 2 1;
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi";
S_0x7f7a4de099a0 .scope module, "led" "led" 2 1;
.timescale 0 0;
.port_info 0 /INPUT 1 "key";
.port_info 1 /OUTPUT 1 "led";
o00000129b78b72a8 .functor BUFZ 1, C4<z>; HiZ drive
L_00000129b78a4e80 .functor BUFZ 1, o00000129b78b72a8, C4<0>, C4<0>, C4<0>;
L_00000129b78ff920 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
v00000129b78a7900_0 .net *"_ivl_17", 1 0, L_00000129b78ff920; 1 drivers
L_00000129b78ff968 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
v00000129b78a7720_0 .net *"_ivl_21", 1 0, L_00000129b78ff968; 1 drivers
v00000129b78a7b80_0 .net *"_ivl_25", 1 0, L_00000129b78b1f80; 1 drivers
v00000129b78a7680_0 .net *"_ivl_27", 0 0, L_00000129b78b0860; 1 drivers
v00000129b78a79a0_0 .net *"_ivl_29", 0 0, L_00000129b78b1120; 1 drivers
v00000129b78a7e00_0 .net *"_ivl_3", 0 0, L_00000129b78a4e80; 1 drivers
L_00000129b78ff9b0 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
v00000129b78a7a40_0 .net *"_ivl_35", 1 0, L_00000129b78ff9b0; 1 drivers
L_00000129b78ff9f8 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
v00000129b78a77c0_0 .net *"_ivl_39", 1 0, L_00000129b78ff9f8; 1 drivers
v00000129b78a7ae0_0 .net *"_ivl_43", 1 0, L_00000129b78b0fe0; 1 drivers
o00000129b78b7188 .functor BUFZ 4, C4<zzzz>; HiZ drive
; Elide local net with no drivers, v00000129b78a7860_0 name=_ivl_49
v00000129b78a8440_0 .net *"_ivl_7", 0 0, L_00000129b78a7fe0; 1 drivers
L_00000129b78ff890 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v00000129b78a7cc0_0 .net "a", 0 0, L_00000129b78ff890; 1 drivers
L_00000129b78ff8d8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v00000129b78a7d60_0 .net "b", 0 0, L_00000129b78ff8d8; 1 drivers
L_00000129b78ff848 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v00000129b78a81c0_0 .net "c", 0 0, L_00000129b78ff848; 1 drivers
v00000129b78a7ea0_0 .net "d", 0 0, L_00000129b78a75e0; 1 drivers
v00000129b78a7540_0 .net "key", 0 0, o00000129b78b72a8; 0 drivers
v00000129b78a7f40_0 .var "led", 0 0;
v00000129b78a8120_0 .net "ret", 1 0, L_00000129b78b1620; 1 drivers
v00000129b78a8080_0 .net "s", 0 0, L_00000129b78a83a0; 1 drivers
v00000129b78a8260_0 .var "v_reg", 5 0;
v00000129b78a8300_0 .net "v_wire", 5 0, L_00000129b78b1da0; 1 drivers
E_00000129b79dc2b0 .event anyedge, v00000129b78a7540_0;
L_00000129b78a7fe0 .part v00000129b78a8260_0, 1, 1;
L_00000129b78a83a0 .part L_00000129b78b1f80, 1, 1;
L_00000129b78a75e0 .part L_00000129b78b1f80, 0, 1;
L_00000129b78b1f80 .arith/sum 2, L_00000129b78ff920, L_00000129b78ff968;
L_00000129b78b1620 .concat8 [ 1 1 0 0], L_00000129b78b1120, L_00000129b78b0860;
L_00000129b78b0860 .part L_00000129b78b0fe0, 1, 1;
L_00000129b78b1120 .part L_00000129b78b0fe0, 0, 1;
L_00000129b78b0fe0 .arith/sum 2, L_00000129b78ff9b0, L_00000129b78ff9f8;
L_00000129b78b1da0 .concat [ 1 1 4 0], L_00000129b78a4e80, L_00000129b78a7fe0, o00000129b78b7188;
.scope S_00000129b79d9e80;
P_0x7f7a4de09b10 .param/l "WIDTH" 0 2 6, +C4<00000000000000000000000000000101>;
o0x7f7a4dd322d8 .functor BUFZ 1, C4<z>; HiZ drive
L_0x7f7a4de18e80 .functor BUFZ 1, o0x7f7a4dd322d8, C4<0>, C4<0>, C4<0>;
L_0x7f7a4dd630e0 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
v0x7f7a4de06240_0 .net *"_ivl_17", 1 0, L_0x7f7a4dd630e0; 1 drivers
L_0x7f7a4dd63128 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
v0x7f7a4de188f0_0 .net *"_ivl_21", 1 0, L_0x7f7a4dd63128; 1 drivers
v0x7f7a4de18990_0 .net *"_ivl_25", 1 0, L_0x7f7a4de19b40; 1 drivers
v0x7f7a4de18a40_0 .net *"_ivl_27", 0 0, L_0x7f7a4de19d30; 1 drivers
v0x7f7a4de18af0_0 .net *"_ivl_29", 0 0, L_0x7f7a4de19e10; 1 drivers
v0x7f7a4de18be0_0 .net *"_ivl_3", 0 0, L_0x7f7a4de18e80; 1 drivers
L_0x7f7a4dd63170 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
v0x7f7a4de18c90_0 .net *"_ivl_35", 1 0, L_0x7f7a4dd63170; 1 drivers
L_0x7f7a4dd631b8 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
v0x7f7a4de18d40_0 .net *"_ivl_39", 1 0, L_0x7f7a4dd631b8; 1 drivers
v0x7f7a4de18df0_0 .net *"_ivl_43", 1 0, L_0x7f7a4de19f70; 1 drivers
o0x7f7a4dd321b8 .functor BUFZ 4, C4<zzzz>; HiZ drive
; Elide local net with no drivers, v0x7f7a4de18f00_0 name=_ivl_49
v0x7f7a4de18fb0_0 .net *"_ivl_7", 0 0, L_0x7f7a4de19800; 1 drivers
L_0x7f7a4dd63050 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v0x7f7a4de19060_0 .net "a", 0 0, L_0x7f7a4dd63050; 1 drivers
L_0x7f7a4dd63098 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v0x7f7a4de19100_0 .net "b", 0 0, L_0x7f7a4dd63098; 1 drivers
L_0x7f7a4dd63008 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x7f7a4de191a0_0 .net "c", 0 0, L_0x7f7a4dd63008; 1 drivers
v0x7f7a4de19240_0 .net "d", 0 0, L_0x7f7a4de19a40; 1 drivers
v0x7f7a4de192e0_0 .net "key", 0 0, o0x7f7a4dd322d8; 0 drivers
v0x7f7a4de19380_0 .var "led", 0 0;
v0x7f7a4de19510_0 .net "ret", 1 0, L_0x7f7a4de19c60; 1 drivers
v0x7f7a4de195a0_0 .net "s", 0 0, L_0x7f7a4de19960; 1 drivers
v0x7f7a4de19630_0 .var "v_reg", 5 0;
v0x7f7a4de196e0_0 .net "v_wire", 5 0, L_0x7f7a4de1a070; 1 drivers
E_0x7f7a4de062f0 .event anyedge, v0x7f7a4de192e0_0;
L_0x7f7a4de19800 .part v0x7f7a4de19630_0, 1, 1;
L_0x7f7a4de19960 .part L_0x7f7a4de19b40, 1, 1;
L_0x7f7a4de19a40 .part L_0x7f7a4de19b40, 0, 1;
L_0x7f7a4de19b40 .arith/sum 2, L_0x7f7a4dd630e0, L_0x7f7a4dd63128;
L_0x7f7a4de19c60 .concat8 [ 1 1 0 0], L_0x7f7a4de19e10, L_0x7f7a4de19d30;
L_0x7f7a4de19d30 .part L_0x7f7a4de19f70, 1, 1;
L_0x7f7a4de19e10 .part L_0x7f7a4de19f70, 0, 1;
L_0x7f7a4de19f70 .arith/sum 2, L_0x7f7a4dd63170, L_0x7f7a4dd631b8;
L_0x7f7a4de1a070 .concat [ 1 1 4 0], L_0x7f7a4de18e80, L_0x7f7a4de19800, o0x7f7a4dd321b8;
.scope S_0x7f7a4de099a0;
T_0 ;
%wait E_00000129b79dc2b0;
%load/vec4 v00000129b78a7540_0;
%wait E_0x7f7a4de062f0;
%load/vec4 v0x7f7a4de192e0_0;
%nor/r;
%store/vec4 v00000129b78a7f40_0, 0, 1;
%load/vec4 v00000129b78a7540_0;
%store/vec4 v0x7f7a4de19380_0, 0, 1;
%load/vec4 v0x7f7a4de192e0_0;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%store/vec4 v00000129b78a8260_0, 4, 1;
%store/vec4 v0x7f7a4de19630_0, 4, 1;
%jmp T_0;
.thread T_0, $push;
# The file index is used to find the file name in the following table.

4
led/tb_led.v
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@ -18,9 +18,11 @@ initial begin
td_key <= 1'b0;
end
// 例化
// 例化, 并传入一些参数
led u_led(
.key (td_key),
.led (td_led)
// .xx () // 如果还有其他的管脚, 空白表示 不连了, 悬空
);
endmodule

20
nixie_tube/nt.v
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@ -0,0 +1,20 @@
module nt(
output A,
output B,
output C,
output D,
output E,
output F,
output G,
output DP,
output S1,
output S2,
output S3,
output S4
);
assign A = 1'b1;
assign B = 1'b1;
assign S1 = 1'b0;
endmodule

22
nixie_tube/nt.v.out
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@ -0,0 +1,22 @@
#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp
:ivl_version "12.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi";
S_0x7f842a7062b0 .scope module, "nt" "nt" 2 23;
.timescale 0 0;
.port_info 0 /OUTPUT 1 "A";
.port_info 1 /OUTPUT 1 "B";
L_0x7f842b363008 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v0x7f842a706420_0 .net "A", 0 0, L_0x7f842b363008; 1 drivers
L_0x7f842b363050 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v0x7f842b10a5a0_0 .net "B", 0 0, L_0x7f842b363050; 1 drivers
# The file index is used to find the file name in the following table.
:file_names 3;
"N/A";
"<interactive>";
"nt.v";
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