From 9a855047562c66992208b5d4c75eb98da354f80e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E9=98=B3=E5=85=89=E5=B0=91=E5=B9=B4?= <849317537@qq.com>
Date: Thu, 16 May 2024 17:05:07 +0800
Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E4=B8=80=E4=B8=AA=E6=97=B6?=
 =?UTF-8?q?=E9=92=9F=E5=80=8D=E9=A2=91=E5=92=8C=E5=88=86=E9=A2=91=E7=9A=84?=
 =?UTF-8?q?=E6=A8=A1=E5=9D=97,=20=E4=B8=8B=E7=8F=AD=E9=9C=80=E8=A6=81?=
 =?UTF-8?q?=E4=BD=BF=E7=94=A8vivado=E4=BB=BF=E7=9C=9F=E6=B5=8B=E8=AF=95?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 clk_wiz/clk_wiz.v    | 32 ++++++++++++++++++++++++++++++++
 clk_wiz/tb_clk_wiz.v | 23 +++++++++++++++++++++++
 2 files changed, 55 insertions(+)
 create mode 100644 clk_wiz/clk_wiz.v
 create mode 100644 clk_wiz/tb_clk_wiz.v

diff --git a/clk_wiz/clk_wiz.v b/clk_wiz/clk_wiz.v
new file mode 100644
index 0000000..75b2020
--- /dev/null
+++ b/clk_wiz/clk_wiz.v
@@ -0,0 +1,32 @@
+// 对时钟信号使用ip核进行分频倍频和偏移
+module clk_wiz(
+    (*mark_debug="true"*)input wire sys_clk,  // U18
+    (*mark_debug="true"*)input wire sys_rst,  //J15
+    (*mark_debug="true"*)output wire clk_100m,
+    (*mark_debug="true"*)output wire clk_100m_r,  // 180度
+    (*mark_debug="true"*)output wire clk_50m,
+    (*mark_debug="true"*)output wire clk_25m
+);
+
+wire locked;  // 内部时钟是否稳定
+wire rst;
+
+// 如果时钟信号稳定之后, 且sys是高电平, 表示板子已经可以正常使用了
+// 其他的例化可以使用该信号 当做是否复位标志
+assign global_rst = locked && sys_rst; 
+
+
+
+clk_wiz_0 u_clk_wiz_0(
+    .clk_in1(sys_clk),
+    .reset(!sys_rst),
+    .clk_out1(clk_100m),
+    .clk_out2(clk_100m_r),
+    .clk_out3(clk_50m),
+    .clk_out4(clk_25m)
+);
+
+
+
+
+endmodule
\ No newline at end of file
diff --git a/clk_wiz/tb_clk_wiz.v b/clk_wiz/tb_clk_wiz.v
new file mode 100644
index 0000000..2f5fee2
--- /dev/null
+++ b/clk_wiz/tb_clk_wiz.v
@@ -0,0 +1,23 @@
+`timescale 1ns/1ns
+module tb_clk_wiz();
+
+reg sys_clk;
+reg sys_rst;
+
+always #10 sys_clk = ~sys_clk;
+
+wire clk_100m;
+wire clk_100m_r;
+wire clk_50m;
+wire clk_25m;
+
+clk_wiz u_clk_wiz(
+    .sys_clk(sys_clk),  // U18
+    .sys_rst(sys_rst),  //J15
+    .clk_100m(clk_100m),
+    .clk_100m_r(clk_100m_r),  // 180度
+    .clk_50m(clk_50m),
+    .clk_25m(clk_25m)
+);
+
+endmodule