From a6465c3f554476e929b68f1273612e6939cf0262 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E9=98=B3=E5=85=89=E5=B0=91=E5=B9=B4?= <849317537@qq.com> Date: Sun, 12 May 2024 14:57:05 +0800 Subject: [PATCH] =?UTF-8?q?=E6=95=B0=E7=A0=81=E7=AE=A1=E6=88=90=E5=8A=9F?= =?UTF-8?q?=E7=82=B9=E4=BA=AE?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- digital_tube/dt.v | 34 ++++++++++++++++++++++++++++ digital_tube/dt.v.out | 52 +++++++++++++++++++++++++++++++++++++++++++ nixie_tube/nt.v | 20 ----------------- nixie_tube/nt.v.out | 22 ------------------ 4 files changed, 86 insertions(+), 42 deletions(-) create mode 100644 digital_tube/dt.v create mode 100644 digital_tube/dt.v.out delete mode 100644 nixie_tube/nt.v delete mode 100755 nixie_tube/nt.v.out diff --git a/digital_tube/dt.v b/digital_tube/dt.v new file mode 100644 index 0000000..71b05c2 --- /dev/null +++ b/digital_tube/dt.v @@ -0,0 +1,34 @@ +// f20 f19 b20 c20 j16 k16 m18 m17 l17 l16 l15 l14 m15 m14 +// 7 8 9 10 11 12 6 5 4 3 2 1 +// B S3 S2 F A S1 S4 G C DP D E +module dt( + output wire A, B, C, D, E, F, G, DP, + output wire S1, S2, S3, S4 +); + +parameter SELECT_1 = 4'b1110; +parameter SELECT_2 = 4'b1101; +parameter SELECT_3 = 4'b1011; +parameter SELECT_4 = 4'b0111; + +// ABCD_EFGP +parameter SHOW_1 = 8'B0110_0000; +parameter SHOW_2 = 8'B1101_1010; +parameter SHOW_3 = 8'B1111_0010; +parameter SHOW_4 = 8'B0110_0110; +parameter SHOW_5 = 8'B1111_1110; +parameter SHOW_6 = 8'B1111_1110; +parameter SHOW_7 = 8'B1111_1110; +parameter SHOW_8 = 8'B1111_1110; +parameter SHOW_9 = 8'B1111_1110; +parameter SHOW_0 = 8'B1111_1110; + + + + +assign {S4, S3, S2, S1} = SELECT_1; +assign {A, B, C, D, E, F, G, DP} = SHOW_1; + + + +endmodule \ No newline at end of file diff --git a/digital_tube/dt.v.out b/digital_tube/dt.v.out new file mode 100644 index 0000000..d5f7aab --- /dev/null +++ b/digital_tube/dt.v.out @@ -0,0 +1,52 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "C:\iverilog\lib\ivl\system.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "C:\iverilog\lib\ivl\va_math.vpi"; +S_000001a9677564a0 .scope module, "dt" "dt" 2 4; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "B"; + .port_info 1 /OUTPUT 1 "S3"; + .port_info 2 /OUTPUT 1 "S2"; + .port_info 3 /OUTPUT 1 "F"; + .port_info 4 /OUTPUT 1 "A"; + .port_info 5 /OUTPUT 1 "S1"; + .port_info 6 /OUTPUT 1 "S4"; + .port_info 7 /OUTPUT 1 "G"; + .port_info 8 /OUTPUT 1 "C"; + .port_info 9 /OUTPUT 1 "DP"; + .port_info 10 /OUTPUT 1 "D"; + .port_info 11 /OUTPUT 1 "E"; +o000001a9678e6fd8 .functor BUFZ 1, C4; HiZ drive +v000001a9677569d0_0 .net "A", 0 0, o000001a9678e6fd8; 0 drivers +o000001a9678e7008 .functor BUFZ 1, C4; HiZ drive +v000001a967756700_0 .net "B", 0 0, o000001a9678e7008; 0 drivers +o000001a9678e7038 .functor BUFZ 1, C4; HiZ drive +v000001a96775d980_0 .net "C", 0 0, o000001a9678e7038; 0 drivers +o000001a9678e7068 .functor BUFZ 1, C4; HiZ drive +v000001a96775da20_0 .net "D", 0 0, o000001a9678e7068; 0 drivers +o000001a9678e7098 .functor BUFZ 1, C4; HiZ drive +v000001a96775dac0_0 .net "DP", 0 0, o000001a9678e7098; 0 drivers +o000001a9678e70c8 .functor BUFZ 1, C4; HiZ drive +v000001a96775db60_0 .net "E", 0 0, o000001a9678e70c8; 0 drivers +o000001a9678e70f8 .functor BUFZ 1, C4; HiZ drive +v000001a96775dc00_0 .net "F", 0 0, o000001a9678e70f8; 0 drivers +o000001a9678e7128 .functor BUFZ 1, C4; HiZ drive +v000001a96775dca0_0 .net "G", 0 0, o000001a9678e7128; 0 drivers +o000001a9678e7158 .functor BUFZ 1, C4; HiZ drive +v000001a96775dd40_0 .net "S1", 0 0, o000001a9678e7158; 0 drivers +o000001a9678e7188 .functor BUFZ 1, C4; HiZ drive +v000001a96775de70_0 .net "S2", 0 0, o000001a9678e7188; 0 drivers +o000001a9678e71b8 .functor BUFZ 1, C4; HiZ drive +v000001a96775df10_0 .net "S3", 0 0, o000001a9678e71b8; 0 drivers +o000001a9678e71e8 .functor BUFZ 1, C4; HiZ drive +v000001a96775dfb0_0 .net "S4", 0 0, o000001a9678e71e8; 0 drivers +# The file index is used to find the file name in the following table. +:file_names 3; + "N/A"; + ""; + "dt.v"; diff --git a/nixie_tube/nt.v b/nixie_tube/nt.v deleted file mode 100644 index e08154f..0000000 --- a/nixie_tube/nt.v +++ /dev/null @@ -1,20 +0,0 @@ -module nt( - output A, - output B, - output C, - output D, - output E, - output F, - output G, - output DP, - output S1, - output S2, - output S3, - output S4 -); - -assign A = 1'b1; -assign B = 1'b1; - -assign S1 = 1'b0; -endmodule \ No newline at end of file diff --git a/nixie_tube/nt.v.out b/nixie_tube/nt.v.out deleted file mode 100755 index 89719c7..0000000 --- a/nixie_tube/nt.v.out +++ /dev/null @@ -1,22 +0,0 @@ -#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp -:ivl_version "12.0 (stable)"; -:ivl_delay_selection "TYPICAL"; -:vpi_time_precision + 0; -:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi"; -:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi"; -:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi"; -:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi"; -:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi"; -S_0x7f842a7062b0 .scope module, "nt" "nt" 2 23; - .timescale 0 0; - .port_info 0 /OUTPUT 1 "A"; - .port_info 1 /OUTPUT 1 "B"; -L_0x7f842b363008 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; -v0x7f842a706420_0 .net "A", 0 0, L_0x7f842b363008; 1 drivers -L_0x7f842b363050 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; -v0x7f842b10a5a0_0 .net "B", 0 0, L_0x7f842b363050; 1 drivers -# The file index is used to find the file name in the following table. -:file_names 3; - "N/A"; - ""; - "nt.v";