防抖设计

main
阳光少年 8 months ago
parent d374da4d97
commit c1859093ec

@ -2,6 +2,7 @@
module tb_lm();
reg k_1; // 1
reg k_2; // 2
@ -10,13 +11,17 @@ reg key; // 物理按键 开关显示, 该按键异步的, 每次按下 等于
reg key_1; //
reg key_2; //
reg is_show; //
reg [4:0] flag_time;
reg flag; // 500ns,
reg flag; // 500,
reg sys_clk;
reg sys_rst;
reg [7:0]x;
reg [7:0]y;
always #10 sys_clk = ~sys_clk;
initial begin
@ -28,11 +33,21 @@ initial begin
// 2000, x 0
#2000
// key, 188
key <= 1'b1;
#188
#120
key <= 1'b0;
#400
#20
key <= 1'b1;
#80
key <= 1'b0;
#20
key <= 1'b1;
#90
key <= 1'b0;
#20
// 4000
{k_2, k_1} <= 2'b10;
@ -40,29 +55,53 @@ initial begin
{k_2, k_1} <= 2'b01;
#3800
// key, 288, , x0
key <= 1'b1;
#20
key <= 1'b0;
#20
key <= 1'b1;
#288
#20
key <= 1'b0;
#20
key <= 1'b1;
#90
key <= 1'b0;
#200
key <= 1'b1;
#120
key <= 1'b0;
#20
key <= 1'b1;
#120
key <= 1'b0;
#20
key <= 1'b1;
#150
key <= 1'b0;
end
reg [5:0] CNT;
//
always @(posedge sys_clk or negedge sys_rst) begin
if (sys_rst == 1'b0) begin
CNT <= 5'd0;
flag_time <= 5'd0;
end
else if (CNT < (5'd25 - 5'd1)) begin
CNT <= CNT + 5'd1;
else if (flag_time < (5'd25 - 5'd1) && is_show) begin
flag_time <= flag_time + 5'd1;
end
else begin
CNT <= 5'b0;
flag_time <= 5'b0;
end
end
reg [7:0]x;
reg [7:0]y;
always @(posedge sys_clk or negedge sys_rst) begin
if (sys_rst == 1'b0) begin
{k_2, k_1} <= 2'b11;
@ -86,11 +125,12 @@ always @(posedge sys_clk or negedge sys_rst) begin
end
end
// 500ns
always @(posedge sys_clk or negedge sys_rst) begin
if (sys_rst == 1'b0) begin
flag <= 1'b0;
end
else if (CNT == (5'd25 - 5'd1)) begin
else if (flag_time == (5'd25 - 5'd1)) begin
flag <= !flag;
end
else begin
@ -112,13 +152,47 @@ end
// 沿,
assign is_click = key_1 && !key_2;
// , 20, 10,
reg [4:0] down_time; // max: 10
reg [4:0] click_time; // max: 20
reg is_lock = 1'b0; //
// 使
always @(posedge sys_clk or negedge sys_rst) begin
if (sys_rst == 1'b0) begin
is_show <= 1'b0;
down_time <= 5'd0;
click_time <= 5'd0;
end
//
else if (is_click) begin
is_show <= !is_show;
is_lock <= 1'b1;
end
else begin
end
// , ,
if (is_lock && click_time == 5'd20 - 5'd1) begin
is_lock <= 1'b0;
click_time <= 5'd0;
down_time <= 5'd0;
//
if (down_time > 5'd10 - 5'd1) begin
is_show <= !is_show;
end
else begin
end
end
//
else if (is_lock && click_time < 5'd20 - 5'd1) begin
click_time <= click_time + 5'd1;
//
if (key_1) begin
down_time <= down_time + 1'd1;
end
else begin
end
end
else begin
end

@ -0,0 +1,75 @@
#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp
:ivl_version "12.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 9;
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi";
S_0x7f94c3905560 .scope module, "tb_lm" "tb_lm" 2 3;
.timescale -9 -9;
v0x7f94c390a240_0 .var "k_1", 0 0;
v0x7f94c3919630_0 .var "k_2", 0 0;
v0x7f94c39196d0_0 .var "key", 0 0;
v0x7f94c3919760_0 .var "sys_clk", 0 0;
v0x7f94c3919800_0 .var "sys_rst", 0 0;
.scope S_0x7f94c3905560;
T_0 ;
%delay 10, 0;
%load/vec4 v0x7f94c3919760_0;
%inv;
%store/vec4 v0x7f94c3919760_0, 0, 1;
%jmp T_0;
.thread T_0;
.scope S_0x7f94c3905560;
T_1 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x7f94c3919760_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x7f94c3919800_0, 0;
%delay 200, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x7f94c3919800_0, 0;
%delay 2000, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x7f94c39196d0_0, 0;
%delay 2, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x7f94c39196d0_0, 0;
%delay 2, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x7f94c39196d0_0, 0;
%delay 2, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x7f94c39196d0_0, 0;
%delay 2, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x7f94c39196d0_0, 0;
%delay 2, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x7f94c39196d0_0, 0;
%delay 2, 0;
%pushi/vec4 2, 0, 2;
%split/vec4 1;
%assign/vec4 v0x7f94c390a240_0, 0;
%assign/vec4 v0x7f94c3919630_0, 0;
%delay 3900, 0;
%pushi/vec4 1, 0, 2;
%split/vec4 1;
%assign/vec4 v0x7f94c390a240_0, 0;
%assign/vec4 v0x7f94c3919630_0, 0;
%delay 3800, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x7f94c39196d0_0, 0;
%delay 2, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x7f94c39196d0_0, 0;
%delay 2, 0;
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 3;
"N/A";
"<interactive>";
"tb_lm_2.v";
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