From c223828a2b4e109058e5cbec1dd181c0ae77c66c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E9=98=B3=E5=85=89=E5=B0=91=E5=B9=B4?= <849317537@qq.com>
Date: Sat, 11 May 2024 09:28:42 +0800
Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E4=B8=80=E4=B8=AAdip?=
 =?UTF-8?q?=E6=8E=A7=E5=88=B6?=
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---
 dip/dip.v     |  8 ++++++++
 dip/dip.v.out | 22 ++++++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 dip/dip.v
 create mode 100755 dip/dip.v.out

diff --git a/dip/dip.v b/dip/dip.v
new file mode 100644
index 0000000..4f68a99
--- /dev/null
+++ b/dip/dip.v
@@ -0,0 +1,8 @@
+module dip(
+    input dip1,  // f20
+    input led  // g14
+);
+
+assign led = !dip1;
+
+endmodule
\ No newline at end of file
diff --git a/dip/dip.v.out b/dip/dip.v.out
new file mode 100755
index 0000000..f54ccbe
--- /dev/null
+++ b/dip/dip.v.out
@@ -0,0 +1,22 @@
+#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp
+:ivl_version "12.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi";
+S_0x7fa85fb046a0 .scope module, "dip" "dip" 2 1;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "dip1";
+    .port_info 1 /INPUT 1 "led";
+o0x7fa85fa32008 .functor BUFZ 1, C4<z>; HiZ drive
+v0x7fa85fb04840_0 .net "dip1", 0 0, o0x7fa85fa32008;  0 drivers
+v0x7fa85fb148b0_0 .net "led", 0 0, L_0x7fa85ef05c70;  1 drivers
+L_0x7fa85ef05c70 .reduce/nor o0x7fa85fa32008;
+# The file index is used to find the file name in the following table.
+:file_names 3;
+    "N/A";
+    "<interactive>";
+    "dip.v";