diff --git a/README.md b/README.md
deleted file mode 100644
index a8f48da..0000000
--- a/README.md
+++ /dev/null
@@ -1,2 +0,0 @@
-# verilog_stu
-
diff --git a/digital_tube/dt.v b/digital_tube/dt.v
index 1769424..4fd8708 100644
--- a/digital_tube/dt.v
+++ b/digital_tube/dt.v
@@ -18,7 +18,7 @@ parameter _SHOW_5 = 8'B1011011;
 parameter _SHOW_6 = 8'B1011111;
 parameter _SHOW_7 = 8'B1110000;
 parameter _SHOW_8 = 8'B1111111;
-parameter _SHOW_9 = 8'B1111101;
+parameter _SHOW_9 = 8'B1110011;
 parameter _SHOW_A = 8'B1110111;
 parameter _SHOW_B = 8'B0011111;
 parameter _SHOW_C = 8'B1001110;
diff --git a/digital_tube/test.v b/digital_tube/test.v
new file mode 100644
index 0000000..9cf7a64
--- /dev/null
+++ b/digital_tube/test.v
@@ -0,0 +1,56 @@
+module test_dt(
+    input wire sys_clk,  // U18
+    input wire sys_rst,  //J15
+    output wire A, B, C, D, E, F, G, DP,
+    output wire S1, S2, S3, S4
+);
+
+
+reg [25:0] CNT;
+
+always @(posedge sys_clk or negedge sys_rst) begin
+    if (sys_rst == 1'b0) begin
+        CNT <= 25'd0;
+    end
+    else if (CNT < (25'd25000000 - 25'd1)) begin
+        CNT <= CNT + 25'd1;
+    end
+    else begin
+        CNT <= 25'b0;
+    end
+end
+
+
+
+reg [7:0] data;
+always @(posedge sys_clk or negedge sys_rst) begin
+    if (sys_rst == 1'b0) begin 
+        data <= 8'b1_00_0_0000;
+    end
+    else if (CNT == (25'd25000000 - 25'd1)) begin
+        data[3:0] <= data[3:0] + 4'b1;
+        data[6:5] <= data[6:5] + 2'b1;
+    end
+    else begin
+
+    end
+end
+
+
+dt u_dt(
+    .data (data),
+    .A (A),
+    .B (B),
+    .C (C),
+    .D (D),
+    .E (E),
+    .F (F),
+    .G (G),
+    .DP (DP),
+    .S1 (S1),
+    .S2 (S2),
+    .S3 (S3),
+    .S4 (S4)
+);
+
+endmodule
\ No newline at end of file