From e24c464e78dacb91b7f13a38d6e64d49a7fdfd97 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E9=98=B3=E5=85=89=E5=B0=91=E5=B9=B4?= <849317537@qq.com>
Date: Fri, 10 May 2024 18:35:04 +0800
Subject: [PATCH] =?UTF-8?q?38=E8=AF=91=E7=A0=81=E5=99=A8=E5=92=8Cled?=
 =?UTF-8?q?=E5=AE=8C=E6=88=90?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 38decoder.v     |  35 ++++++
 38decoder.v.out | 292 ++++++++++++++++++++++++++++++++++++++++++++++++
 led.v           |  42 +++++++
 led.v.out       |  71 ++++++++++++
 4 files changed, 440 insertions(+)
 create mode 100644 38decoder.v
 create mode 100755 38decoder.v.out
 create mode 100644 led.v
 create mode 100755 led.v.out

diff --git a/38decoder.v b/38decoder.v
new file mode 100644
index 0000000..b4edc94
--- /dev/null
+++ b/38decoder.v
@@ -0,0 +1,35 @@
+module decoder38(
+    input wire [2:0]i,
+    output wire [7:0]o
+);
+
+// 直接使用门电路连线
+wire [7:0] w_o;
+assign w_o[0] = i[0] && i[1] && i[2];
+assign w_o[1] = !i[0] && i[1] && i[2];
+assign w_o[2] = i[0] && !i[1] && i[2];
+assign w_o[3] = !i[0] && !i[1] && i[2];
+assign w_o[4] = i[0] && i[1] && !i[2];
+assign w_o[5] = !i[0] && i[1] && !i[2];
+assign w_o[6] = i[0] && !i[1] && !i[2];
+assign w_o[7] = !i[0] && !i[1] && !i[2];
+assign o = w_o;
+
+// 使用 always 连线
+reg [7:0]r_o;
+always @(i) begin
+    // 阻塞赋值
+    r_o[0] = i[0] && i[1] && i[2];
+    r_o[1] = !i[0] && i[1] && i[2];
+    r_o[2] = i[0] && !i[1] && i[2];
+    r_o[3] = !i[0] && !i[1] && i[2];
+
+    // 非阻塞赋值, 他们是并行连线的
+    r_o[4] <= i[0] && i[1] && !i[2];
+    r_o[5] <= !i[0] && i[1] && !i[2];
+    r_o[6] <=  i == 3'b001;  // i[0] && !i[1] && !i[2];
+    r_o[7] <= !i[0] && !i[1] && !i[2];
+end
+assign o=r_o;
+
+endmodule
\ No newline at end of file
diff --git a/38decoder.v.out b/38decoder.v.out
new file mode 100755
index 0000000..d9a5df9
--- /dev/null
+++ b/38decoder.v.out
@@ -0,0 +1,292 @@
+#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp
+:ivl_version "12.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi";
+S_0x7f91b39054b0 .scope module, "decoder38" "decoder38" 2 1;
+ .timescale 0 0;
+    .port_info 0 /INPUT 3 "i";
+    .port_info 1 /OUTPUT 8 "o";
+L_0x7f91b39163f0 .functor AND 1, L_0x7f91b3916210, L_0x7f91b39162f0, C4<1>, C4<1>;
+L_0x7f91b39165a0 .functor AND 1, L_0x7f91b39163f0, L_0x7f91b3916500, C4<1>, C4<1>;
+L_0x7f91b3916960 .functor AND 1, L_0x7f91b39167f0, L_0x7f91b39168c0, C4<1>, C4<1>;
+L_0x7f91b3916b50 .functor AND 1, L_0x7f91b3916960, L_0x7f91b3916a70, C4<1>, C4<1>;
+L_0x7f91b3916770 .functor AND 1, L_0x7f91b3916c80, L_0x7f91b3916f10, C4<1>, C4<1>;
+L_0x7f91b3917180 .functor AND 1, L_0x7f91b3916770, L_0x7f91b3917080, C4<1>, C4<1>;
+L_0x7f91b39173b0 .functor AND 1, L_0x7f91b39172d0, L_0x7f91b39174c0, C4<1>, C4<1>;
+L_0x7f91b3917760 .functor AND 1, L_0x7f91b39173b0, L_0x7f91b39176c0, C4<1>, C4<1>;
+L_0x7f91b39179b0 .functor AND 1, L_0x7f91b3917850, L_0x7f91b39178f0, C4<1>, C4<1>;
+L_0x7f91b3917c70 .functor AND 1, L_0x7f91b39179b0, L_0x7f91b3917bd0, C4<1>, C4<1>;
+L_0x7f91b3918180 .functor AND 1, L_0x7f91b3917560, L_0x7f91b3918020, C4<1>, C4<1>;
+L_0x7f91b39184a0 .functor AND 1, L_0x7f91b3918180, L_0x7f91b3918330, C4<1>, C4<1>;
+L_0x7f91b3918410 .functor AND 1, L_0x7f91b3918510, L_0x7f91b3918730, C4<1>, C4<1>;
+L_0x7f91b3918650 .functor AND 1, L_0x7f91b3918410, L_0x7f91b3918a50, C4<1>, C4<1>;
+L_0x7f91b3919180 .functor AND 1, L_0x7f91b3918f80, L_0x7f91b3918de0, C4<1>, C4<1>;
+L_0x7f91b3918850 .functor AND 1, L_0x7f91b3919180, L_0x7f91b3919350, C4<1>, C4<1>;
+L_0x7f91b3919560 .functor BUFZ 8, L_0x7f91b3918b30, C4<00000000>, C4<00000000>, C4<00000000>;
+v0x7f91b3905620_0 .net *"_ivl_101", 0 0, L_0x7f91b3918650;  1 drivers
+v0x7f91b3b051b0_0 .net *"_ivl_106", 0 0, L_0x7f91b3918ee0;  1 drivers
+v0x7f91b3b05270_0 .net *"_ivl_108", 0 0, L_0x7f91b3918f80;  1 drivers
+v0x7f91b3b05300_0 .net *"_ivl_11", 0 0, L_0x7f91b39165a0;  1 drivers
+v0x7f91b3b053a0_0 .net *"_ivl_110", 0 0, L_0x7f91b3918960;  1 drivers
+v0x7f91b3b05490_0 .net *"_ivl_112", 0 0, L_0x7f91b3918de0;  1 drivers
+v0x7f91b3b05530_0 .net *"_ivl_114", 0 0, L_0x7f91b3919180;  1 drivers
+v0x7f91b3b055d0_0 .net *"_ivl_116", 0 0, L_0x7f91b39192b0;  1 drivers
+v0x7f91b3b05680_0 .net *"_ivl_118", 0 0, L_0x7f91b3919350;  1 drivers
+v0x7f91b3b05790_0 .net *"_ivl_120", 0 0, L_0x7f91b3918850;  1 drivers
+v0x7f91b3b05820_0 .net *"_ivl_15", 0 0, L_0x7f91b39166d0;  1 drivers
+v0x7f91b3b058d0_0 .net *"_ivl_17", 0 0, L_0x7f91b39167f0;  1 drivers
+v0x7f91b3b05970_0 .net *"_ivl_19", 0 0, L_0x7f91b39168c0;  1 drivers
+v0x7f91b3b05a20_0 .net *"_ivl_21", 0 0, L_0x7f91b3916960;  1 drivers
+v0x7f91b3b05ac0_0 .net *"_ivl_23", 0 0, L_0x7f91b3916a70;  1 drivers
+v0x7f91b3b05b70_0 .net *"_ivl_25", 0 0, L_0x7f91b3916b50;  1 drivers
+v0x7f91b3b05c10_0 .net *"_ivl_29", 0 0, L_0x7f91b3916c80;  1 drivers
+v0x7f91b3b05da0_0 .net *"_ivl_3", 0 0, L_0x7f91b3916210;  1 drivers
+v0x7f91b3b05e30_0 .net *"_ivl_31", 0 0, L_0x7f91b3916d20;  1 drivers
+v0x7f91b3b05ee0_0 .net *"_ivl_33", 0 0, L_0x7f91b3916f10;  1 drivers
+v0x7f91b3b05f80_0 .net *"_ivl_35", 0 0, L_0x7f91b3916770;  1 drivers
+v0x7f91b39148f0_0 .net *"_ivl_37", 0 0, L_0x7f91b3917080;  1 drivers
+v0x7f91b3914980_0 .net *"_ivl_39", 0 0, L_0x7f91b3917180;  1 drivers
+v0x7f91b3914a20_0 .net *"_ivl_43", 0 0, L_0x7f91b3917230;  1 drivers
+v0x7f91b3914ad0_0 .net *"_ivl_45", 0 0, L_0x7f91b39172d0;  1 drivers
+v0x7f91b3914b70_0 .net *"_ivl_47", 0 0, L_0x7f91b3917420;  1 drivers
+v0x7f91b3914c20_0 .net *"_ivl_49", 0 0, L_0x7f91b39174c0;  1 drivers
+v0x7f91b3914cc0_0 .net *"_ivl_5", 0 0, L_0x7f91b39162f0;  1 drivers
+v0x7f91b3914d70_0 .net *"_ivl_51", 0 0, L_0x7f91b39173b0;  1 drivers
+v0x7f91b3914e10_0 .net *"_ivl_53", 0 0, L_0x7f91b39176c0;  1 drivers
+v0x7f91b3914ec0_0 .net *"_ivl_55", 0 0, L_0x7f91b3917760;  1 drivers
+v0x7f91b3914f60_0 .net *"_ivl_59", 0 0, L_0x7f91b3917850;  1 drivers
+v0x7f91b3915010_0 .net *"_ivl_61", 0 0, L_0x7f91b39178f0;  1 drivers
+v0x7f91b39152c0_0 .net *"_ivl_63", 0 0, L_0x7f91b39179b0;  1 drivers
+v0x7f91b3915360_0 .net *"_ivl_65", 0 0, L_0x7f91b3917b30;  1 drivers
+v0x7f91b3915410_0 .net *"_ivl_67", 0 0, L_0x7f91b3917bd0;  1 drivers
+v0x7f91b39154b0_0 .net *"_ivl_69", 0 0, L_0x7f91b3917c70;  1 drivers
+v0x7f91b3915550_0 .net *"_ivl_7", 0 0, L_0x7f91b39163f0;  1 drivers
+v0x7f91b39155f0_0 .net *"_ivl_73", 0 0, L_0x7f91b3917d80;  1 drivers
+v0x7f91b39156a0_0 .net *"_ivl_75", 0 0, L_0x7f91b3917560;  1 drivers
+v0x7f91b3915740_0 .net *"_ivl_77", 0 0, L_0x7f91b3918020;  1 drivers
+v0x7f91b39157f0_0 .net *"_ivl_79", 0 0, L_0x7f91b3918180;  1 drivers
+v0x7f91b3915890_0 .net *"_ivl_81", 0 0, L_0x7f91b3918290;  1 drivers
+v0x7f91b3915940_0 .net *"_ivl_83", 0 0, L_0x7f91b3918330;  1 drivers
+v0x7f91b39159e0_0 .net *"_ivl_85", 0 0, L_0x7f91b39184a0;  1 drivers
+v0x7f91b3915a80_0 .net *"_ivl_89", 0 0, L_0x7f91b3918510;  1 drivers
+v0x7f91b3915b30_0 .net *"_ivl_9", 0 0, L_0x7f91b3916500;  1 drivers
+v0x7f91b3915be0_0 .net *"_ivl_91", 0 0, L_0x7f91b39185b0;  1 drivers
+v0x7f91b3915c90_0 .net *"_ivl_93", 0 0, L_0x7f91b3918730;  1 drivers
+v0x7f91b3915d30_0 .net *"_ivl_95", 0 0, L_0x7f91b3918410;  1 drivers
+v0x7f91b3915dd0_0 .net *"_ivl_97", 0 0, L_0x7f91b39188c0;  1 drivers
+v0x7f91b3915e80_0 .net *"_ivl_99", 0 0, L_0x7f91b3918a50;  1 drivers
+o0x7f91b3a329c8 .functor BUFZ 3, C4<zzz>; HiZ drive
+v0x7f91b3915f20_0 .net "i", 2 0, o0x7f91b3a329c8;  0 drivers
+RS_0x7f91b3a329f8 .resolv tri, L_0x7f91b3919560, v0x7f91b3916080_0;
+v0x7f91b3915fd0_0 .net8 "o", 7 0, RS_0x7f91b3a329f8;  2 drivers
+v0x7f91b3916080_0 .var "r_o", 7 0;
+v0x7f91b3916130_0 .net "w_o", 7 0, L_0x7f91b3918b30;  1 drivers
+E_0x7f91b3905010 .event anyedge, v0x7f91b3915f20_0;
+L_0x7f91b3916210 .part o0x7f91b3a329c8, 0, 1;
+L_0x7f91b39162f0 .part o0x7f91b3a329c8, 1, 1;
+L_0x7f91b3916500 .part o0x7f91b3a329c8, 2, 1;
+L_0x7f91b39166d0 .part o0x7f91b3a329c8, 0, 1;
+L_0x7f91b39167f0 .reduce/nor L_0x7f91b39166d0;
+L_0x7f91b39168c0 .part o0x7f91b3a329c8, 1, 1;
+L_0x7f91b3916a70 .part o0x7f91b3a329c8, 2, 1;
+L_0x7f91b3916c80 .part o0x7f91b3a329c8, 0, 1;
+L_0x7f91b3916d20 .part o0x7f91b3a329c8, 1, 1;
+L_0x7f91b3916f10 .reduce/nor L_0x7f91b3916d20;
+L_0x7f91b3917080 .part o0x7f91b3a329c8, 2, 1;
+L_0x7f91b3917230 .part o0x7f91b3a329c8, 0, 1;
+L_0x7f91b39172d0 .reduce/nor L_0x7f91b3917230;
+L_0x7f91b3917420 .part o0x7f91b3a329c8, 1, 1;
+L_0x7f91b39174c0 .reduce/nor L_0x7f91b3917420;
+L_0x7f91b39176c0 .part o0x7f91b3a329c8, 2, 1;
+L_0x7f91b3917850 .part o0x7f91b3a329c8, 0, 1;
+L_0x7f91b39178f0 .part o0x7f91b3a329c8, 1, 1;
+L_0x7f91b3917b30 .part o0x7f91b3a329c8, 2, 1;
+L_0x7f91b3917bd0 .reduce/nor L_0x7f91b3917b30;
+L_0x7f91b3917d80 .part o0x7f91b3a329c8, 0, 1;
+L_0x7f91b3917560 .reduce/nor L_0x7f91b3917d80;
+L_0x7f91b3918020 .part o0x7f91b3a329c8, 1, 1;
+L_0x7f91b3918290 .part o0x7f91b3a329c8, 2, 1;
+L_0x7f91b3918330 .reduce/nor L_0x7f91b3918290;
+L_0x7f91b3918510 .part o0x7f91b3a329c8, 0, 1;
+L_0x7f91b39185b0 .part o0x7f91b3a329c8, 1, 1;
+L_0x7f91b3918730 .reduce/nor L_0x7f91b39185b0;
+L_0x7f91b39188c0 .part o0x7f91b3a329c8, 2, 1;
+L_0x7f91b3918a50 .reduce/nor L_0x7f91b39188c0;
+LS_0x7f91b3918b30_0_0 .concat8 [ 1 1 1 1], L_0x7f91b39165a0, L_0x7f91b3916b50, L_0x7f91b3917180, L_0x7f91b3917760;
+LS_0x7f91b3918b30_0_4 .concat8 [ 1 1 1 1], L_0x7f91b3917c70, L_0x7f91b39184a0, L_0x7f91b3918650, L_0x7f91b3918850;
+L_0x7f91b3918b30 .concat8 [ 4 4 0 0], LS_0x7f91b3918b30_0_0, LS_0x7f91b3918b30_0_4;
+L_0x7f91b3918ee0 .part o0x7f91b3a329c8, 0, 1;
+L_0x7f91b3918f80 .reduce/nor L_0x7f91b3918ee0;
+L_0x7f91b3918960 .part o0x7f91b3a329c8, 1, 1;
+L_0x7f91b3918de0 .reduce/nor L_0x7f91b3918960;
+L_0x7f91b39192b0 .part o0x7f91b3a329c8, 2, 1;
+L_0x7f91b3919350 .reduce/nor L_0x7f91b39192b0;
+    .scope S_0x7f91b39054b0;
+T_0 ;
+    %wait E_0x7f91b3905010;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 0, 2;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_0.1, 9;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 1, 2;
+    %and;
+T_0.1;
+    %flag_set/vec4 8;
+    %flag_get/vec4 8;
+    %jmp/0 T_0.0, 8;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 2, 3;
+    %and;
+T_0.0;
+    %ix/load 4, 0, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4 v0x7f91b3916080_0, 4, 1;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 0, 2;
+    %nor/r;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_0.3, 9;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 1, 2;
+    %and;
+T_0.3;
+    %flag_set/vec4 8;
+    %flag_get/vec4 8;
+    %jmp/0 T_0.2, 8;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 2, 3;
+    %and;
+T_0.2;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4 v0x7f91b3916080_0, 4, 1;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 0, 2;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_0.5, 9;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 1, 2;
+    %nor/r;
+    %and;
+T_0.5;
+    %flag_set/vec4 8;
+    %flag_get/vec4 8;
+    %jmp/0 T_0.4, 8;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 2, 3;
+    %and;
+T_0.4;
+    %ix/load 4, 2, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4 v0x7f91b3916080_0, 4, 1;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 0, 2;
+    %nor/r;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_0.7, 9;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 1, 2;
+    %nor/r;
+    %and;
+T_0.7;
+    %flag_set/vec4 8;
+    %flag_get/vec4 8;
+    %jmp/0 T_0.6, 8;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 2, 3;
+    %and;
+T_0.6;
+    %ix/load 4, 3, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4 v0x7f91b3916080_0, 4, 1;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 0, 2;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_0.9, 9;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 1, 2;
+    %and;
+T_0.9;
+    %flag_set/vec4 8;
+    %flag_get/vec4 8;
+    %jmp/0 T_0.8, 8;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 2, 3;
+    %nor/r;
+    %and;
+T_0.8;
+    %ix/load 4, 4, 0;
+    %ix/load 5, 0, 0;
+    %flag_set/imm 4, 0;
+    %assign/vec4/off/d v0x7f91b3916080_0, 4, 5;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 0, 2;
+    %nor/r;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_0.11, 9;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 1, 2;
+    %and;
+T_0.11;
+    %flag_set/vec4 8;
+    %flag_get/vec4 8;
+    %jmp/0 T_0.10, 8;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 2, 3;
+    %nor/r;
+    %and;
+T_0.10;
+    %ix/load 4, 5, 0;
+    %ix/load 5, 0, 0;
+    %flag_set/imm 4, 0;
+    %assign/vec4/off/d v0x7f91b3916080_0, 4, 5;
+    %load/vec4 v0x7f91b3915f20_0;
+    %pushi/vec4 1, 0, 3;
+    %cmp/e;
+    %flag_get/vec4 4;
+    %ix/load 4, 6, 0;
+    %ix/load 5, 0, 0;
+    %flag_set/imm 4, 0;
+    %assign/vec4/off/d v0x7f91b3916080_0, 4, 5;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 0, 2;
+    %nor/r;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_0.13, 9;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 1, 2;
+    %nor/r;
+    %and;
+T_0.13;
+    %flag_set/vec4 8;
+    %flag_get/vec4 8;
+    %jmp/0 T_0.12, 8;
+    %load/vec4 v0x7f91b3915f20_0;
+    %parti/s 1, 2, 3;
+    %nor/r;
+    %and;
+T_0.12;
+    %ix/load 4, 7, 0;
+    %ix/load 5, 0, 0;
+    %flag_set/imm 4, 0;
+    %assign/vec4/off/d v0x7f91b3916080_0, 4, 5;
+    %jmp T_0;
+    .thread T_0, $push;
+# The file index is used to find the file name in the following table.
+:file_names 3;
+    "N/A";
+    "<interactive>";
+    "38decoder.v";
diff --git a/led.v b/led.v
new file mode 100644
index 0000000..237793e
--- /dev/null
+++ b/led.v
@@ -0,0 +1,42 @@
+module led(  // 该括号内对 io口 以及类型 进行说明
+    input key,  // 默认为 wire 型
+    output reg led  // 因为需要再always中改变状态, 需要设置为寄存器型
+);
+
+reg [5:0]v_reg;  // 定义一个 线类型, 宽度为 6bit
+wire [5:0]v_wire;  // 定义一个 寄存器类型, 宽度为 6bit
+
+always @(*) begin  // * 表示内部的任何变量发生变化的时候, 就会并行执行该 block
+                   // 该块 没有带时钟信号, 虽然内部产生的信号定义还是 reg型的, 但是他并没有产生时序逻辑, 还是组合逻辑, 只有带时钟信号之后, 才会使用真正的存储单元/寄存器
+                   // begin ... end 表示改语句是一个块, 块内的语句是一体的, 如果没有begin ... end, 则只会执行 always 下面紧挨着的 1行!
+    led = !key;    // 对reg 类型变量 阻塞赋值, 他执行完毕, 才会执行下面的
+
+    v_reg[1] = key;
+    // v_wire[1] = key;  // 不能 对 wire 类型 进行赋值, wire类型是用来连接各种门的信号线, 他只能使用 assign进行连线
+end
+
+// assign v_reg[0] = key;  // 寄存器类型 不能进行 连线, 他只能在 always中进行赋值
+assign v_wire[0] = key;
+assign v_wire[1] = v_reg[1];  // 把 v_wire 线中 下标1的位置直接连到 v_reg寄存器中的下标1
+
+
+
+// 信号的位宽
+//     信号宽度默认是 1bit, 可以省略不写
+wire c;
+assign c = 1'b1 + 1'b1;  // c的宽度是 1bit, 这个加法溢出了, 溢出的丢失, 所以c 是 1'b0
+
+
+wire a;
+wire b;
+wire d;
+wire s;
+assign a = 1'b1;
+assign b = 1'b1;
+assign {s, d} = a + b;  // 也会溢出, 我们把进位保存起来到 s
+
+wire [1:0]ret;
+assign {ret[1], ret[0]} = a + b;  // 把结果和进位 拼接到位宽为 2 的 ret中
+
+
+endmodule
\ No newline at end of file
diff --git a/led.v.out b/led.v.out
new file mode 100755
index 0000000..598f0ae
--- /dev/null
+++ b/led.v.out
@@ -0,0 +1,71 @@
+#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp
+:ivl_version "12.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi";
+S_0x7f920c80a740 .scope module, "led" "led" 2 1;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "key";
+    .port_info 1 /OUTPUT 1 "led";
+o0x7f920c9322d8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0x7f920c81aae0 .functor BUFZ 1, o0x7f920c9322d8, C4<0>, C4<0>, C4<0>;
+L_0x7f920c9630e0 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
+v0x7f920c805670_0 .net *"_ivl_17", 1 0, L_0x7f920c9630e0;  1 drivers
+L_0x7f920c963128 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
+v0x7f920c81a550_0 .net *"_ivl_21", 1 0, L_0x7f920c963128;  1 drivers
+v0x7f920c81a5f0_0 .net *"_ivl_25", 1 0, L_0x7f920ca06e10;  1 drivers
+v0x7f920c81a6a0_0 .net *"_ivl_27", 0 0, L_0x7f920ca06f50;  1 drivers
+v0x7f920c81a750_0 .net *"_ivl_29", 0 0, L_0x7f920ca06ff0;  1 drivers
+v0x7f920c81a840_0 .net *"_ivl_3", 0 0, L_0x7f920c81aae0;  1 drivers
+L_0x7f920c963170 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
+v0x7f920c81a8f0_0 .net *"_ivl_35", 1 0, L_0x7f920c963170;  1 drivers
+L_0x7f920c9631b8 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
+v0x7f920c81a9a0_0 .net *"_ivl_39", 1 0, L_0x7f920c9631b8;  1 drivers
+v0x7f920c81aa50_0 .net *"_ivl_43", 1 0, L_0x7f920ca07090;  1 drivers
+o0x7f920c9321b8 .functor BUFZ 4, C4<zzzz>; HiZ drive
+; Elide local net with no drivers, v0x7f920c81ab60_0 name=_ivl_49
+v0x7f920c81ac10_0 .net *"_ivl_7", 0 0, L_0x7f920c81b460;  1 drivers
+L_0x7f920c963050 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0x7f920c81acc0_0 .net "a", 0 0, L_0x7f920c963050;  1 drivers
+L_0x7f920c963098 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0x7f920c81ad60_0 .net "b", 0 0, L_0x7f920c963098;  1 drivers
+L_0x7f920c963008 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x7f920c81ae00_0 .net "c", 0 0, L_0x7f920c963008;  1 drivers
+v0x7f920c81aea0_0 .net "d", 0 0, L_0x7f920ca06d70;  1 drivers
+v0x7f920c81af40_0 .net "key", 0 0, o0x7f920c9322d8;  0 drivers
+v0x7f920c81afe0_0 .var "led", 0 0;
+v0x7f920c81b170_0 .net "ret", 1 0, L_0x7f920ca06eb0;  1 drivers
+v0x7f920c81b200_0 .net "s", 0 0, L_0x7f920ca06cd0;  1 drivers
+v0x7f920c81b290_0 .var "v_reg", 5 0;
+v0x7f920c81b340_0 .net "v_wire", 5 0, L_0x7f920ca07130;  1 drivers
+E_0x7f920c80a8b0 .event anyedge, v0x7f920c81af40_0;
+L_0x7f920c81b460 .part v0x7f920c81b290_0, 1, 1;
+L_0x7f920ca06cd0 .part L_0x7f920ca06e10, 1, 1;
+L_0x7f920ca06d70 .part L_0x7f920ca06e10, 0, 1;
+L_0x7f920ca06e10 .arith/sum 2, L_0x7f920c9630e0, L_0x7f920c963128;
+L_0x7f920ca06eb0 .concat8 [ 1 1 0 0], L_0x7f920ca06ff0, L_0x7f920ca06f50;
+L_0x7f920ca06f50 .part L_0x7f920ca07090, 1, 1;
+L_0x7f920ca06ff0 .part L_0x7f920ca07090, 0, 1;
+L_0x7f920ca07090 .arith/sum 2, L_0x7f920c963170, L_0x7f920c9631b8;
+L_0x7f920ca07130 .concat [ 1 1 4 0], L_0x7f920c81aae0, L_0x7f920c81b460, o0x7f920c9321b8;
+    .scope S_0x7f920c80a740;
+T_0 ;
+    %wait E_0x7f920c80a8b0;
+    %load/vec4 v0x7f920c81af40_0;
+    %nor/r;
+    %store/vec4 v0x7f920c81afe0_0, 0, 1;
+    %load/vec4 v0x7f920c81af40_0;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %store/vec4 v0x7f920c81b290_0, 4, 1;
+    %jmp T_0;
+    .thread T_0, $push;
+# The file index is used to find the file name in the following table.
+:file_names 3;
+    "N/A";
+    "<interactive>";
+    "led.v";