From f0caf83860730c264f0dc51804eff1e1612c4f99 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E9=98=B3=E5=85=89=E5=B0=91=E5=B9=B4?= <849317537@qq.com>
Date: Fri, 17 May 2024 00:53:07 +0800
Subject: [PATCH] =?UTF-8?q?=E5=A7=8B=E7=BB=88=E4=BB=BF=E7=9C=9F=E9=80=9A?=
 =?UTF-8?q?=E8=BF=87,=20=E4=B8=8A=E6=9D=BF=E6=B5=8B=E8=AF=95=E5=A4=B1?=
 =?UTF-8?q?=E8=B4=A5=E5=BA=94=E8=AF=A5=E6=98=AF=E4=B8=8D=E8=83=BD=E9=87=87?=
 =?UTF-8?q?=E9=9B=86=E6=95=B4=E5=80=8D=E6=95=B0=E7=9A=84=E6=97=B6=E9=92=9F?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 clk_wiz/clk_wiz.v    | 28 +++++++++++++---------------
 clk_wiz/tb_clk_wiz.v | 11 ++++++++++-
 ip_1_port_ram/ram.v  |  0
 3 files changed, 23 insertions(+), 16 deletions(-)
 create mode 100644 ip_1_port_ram/ram.v

diff --git a/clk_wiz/clk_wiz.v b/clk_wiz/clk_wiz.v
index 75b2020..d45a51e 100644
--- a/clk_wiz/clk_wiz.v
+++ b/clk_wiz/clk_wiz.v
@@ -1,17 +1,17 @@
-// 对时钟信号使用ip核进行分频倍频和偏移
+// 对时钟信号使用ip核进行分频�?�频和偏�?
 module clk_wiz(
-    (*mark_debug="true"*)input wire sys_clk,  // U18
-    (*mark_debug="true"*)input wire sys_rst,  //J15
-    (*mark_debug="true"*)output wire clk_100m,
-    (*mark_debug="true"*)output wire clk_100m_r,  // 180度
-    (*mark_debug="true"*)output wire clk_50m,
-    (*mark_debug="true"*)output wire clk_25m
+    input wire sys_clk,  // U18
+    input wire sys_rst,  //J15
+    (*mark_debug="true"*)output wire clk_100m,  // e19
+    output wire clk_100m_r,  // d19 180�?
+    (*mark_debug="true"*)output wire clk_50m,  // a20
+    (*mark_debug="true"*)output wire clk_25m,  // b19
+    (*mark_debug="true"*)output wire clk_15m  // d20
 );
 
 wire locked;  // 内部时钟是否稳定
-wire rst;
-
-// 如果时钟信号稳定之后, 且sys是高电平, 表示板子已经可以正常使用了
+wire global_rst;
+// 如果时钟信号稳定之后, 且sys是高电平, 表示板子已经可以正常使用�?
 // 其他的例化可以使用该信号 当做是否复位标志
 assign global_rst = locked && sys_rst; 
 
@@ -23,10 +23,8 @@ clk_wiz_0 u_clk_wiz_0(
     .clk_out1(clk_100m),
     .clk_out2(clk_100m_r),
     .clk_out3(clk_50m),
-    .clk_out4(clk_25m)
+    .clk_out4(clk_25m),
+    .clk_out5(clk_15m),
+    .locked(locked)
 );
-
-
-
-
 endmodule
\ No newline at end of file
diff --git a/clk_wiz/tb_clk_wiz.v b/clk_wiz/tb_clk_wiz.v
index 2f5fee2..2ee2bbf 100644
--- a/clk_wiz/tb_clk_wiz.v
+++ b/clk_wiz/tb_clk_wiz.v
@@ -6,10 +6,18 @@ reg sys_rst;
 
 always #10 sys_clk = ~sys_clk;
 
+initial begin
+    sys_clk <= 1'b0;
+    sys_rst <= 1'b0;
+    #50
+    sys_rst <= 1'b1;
+end
+
 wire clk_100m;
 wire clk_100m_r;
 wire clk_50m;
 wire clk_25m;
+wire clk_15m;
 
 clk_wiz u_clk_wiz(
     .sys_clk(sys_clk),  // U18
@@ -17,7 +25,8 @@ clk_wiz u_clk_wiz(
     .clk_100m(clk_100m),
     .clk_100m_r(clk_100m_r),  // 180度
     .clk_50m(clk_50m),
-    .clk_25m(clk_25m)
+    .clk_25m(clk_25m),
+    .clk_15m(clk_15m)
 );
 
 endmodule
diff --git a/ip_1_port_ram/ram.v b/ip_1_port_ram/ram.v
new file mode 100644
index 0000000..e69de29