diff --git a/compute/div.v b/compute/div.v
new file mode 100644
index 0000000..ab52257
--- /dev/null
+++ b/compute/div.v
@@ -0,0 +1,59 @@
+// 在verilog中直接使用 / 进行除法运算, 位数越多, 消耗的资源会非常多, 而且时序 无法控制
+module div(
+    (*mark_debug="true"*)input wire sys_clk,  // U18
+    (*mark_debug="true"*)input wire sys_rst  //J15
+);
+
+
+parameter t_1 = 8;
+(*mark_debug="true"*)reg [t_1-1:0] a_8 = 'b1;
+(*mark_debug="true"*)reg [t_1-1:0] b_8 = 'b1;
+(*mark_debug="true"*) wire o_8 = a_8 / b_8;
+
+always @(posedge sys_clk or  negedge sys_rst) begin
+    if (!sys_rst) begin
+        a_8 <= 'b1;
+        b_8 <= 'b1;
+    end
+    else begin
+        a_8 <= a_8 + 'b1;
+        b_8 <= b_8 + 'b1;
+    end
+end
+
+
+parameter t_2 = 16;
+(*mark_debug="true"*)reg [t_2-1:0] a_16 = 'b1;
+(*mark_debug="true"*)reg [t_2-1:0] b_16 = 'b1;
+(*mark_debug="true"*) wire o_18 = a_16 / b_16;
+
+always @(posedge sys_clk or  negedge sys_rst) begin
+    if (!sys_rst) begin
+        a_16 <= 'b1;
+        b_16 <= 'b1;
+    end
+    else begin
+        a_16 <= a_16 + 'b1;
+        b_16 <= b_16 + 'b1;
+    end
+end
+
+
+
+parameter t_3 = 28;
+(*mark_debug="true"*)reg [t_3-1:0] a_28 = 'b1_1000;
+(*mark_debug="true"*)reg [t_3-1:0] b_28 = 'b1;
+(*mark_debug="true"*) wire o_28 = a_28 / b_28;
+
+always @(posedge sys_clk or  negedge sys_rst) begin
+    if (!sys_rst) begin
+        a_28 <= 'b1;
+        b_28 <= 'b1;
+    end
+    else begin
+        a_28 <= a_28 + 'b1;
+        b_28 <= b_28 + 'b1;
+    end
+end
+
+endmodule
\ No newline at end of file
diff --git a/compute/div.v.out b/compute/div.v.out
new file mode 100755
index 0000000..8855887
--- /dev/null
+++ b/compute/div.v.out
@@ -0,0 +1,95 @@
+#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp
+:ivl_version "12.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi";
+S_0x7fa89ad06690 .scope module, "div" "div" 2 1;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "sys_clk";
+    .port_info 1 /INPUT 1 "sys_rst";
+P_0x7fa89ad057c0 .param/l "t_1" 0 2 7, +C4<00000000000000000000000000001000>;
+P_0x7fa89ad05800 .param/l "t_2" 0 2 24, +C4<00000000000000000000000000010000>;
+v0x7fa89ad06880_0 .net *"_ivl_0", 7 0, L_0x7fa89ad17050;  1 drivers
+v0x7fa89ad168e0_0 .net *"_ivl_4", 15 0, L_0x7fa89ad17210;  1 drivers
+v0x7fa89ad16980_0 .var "a_16", 15 0;
+v0x7fa89ad16ad0_0 .var "a_8", 7 0;
+v0x7fa89ad16ba0_0 .var "b_16", 15 0;
+v0x7fa89ad16cf0_0 .var "b_8", 7 0;
+v0x7fa89ad16d80_0 .net "o_18", 0 0, L_0x7fa89ad172f0;  1 drivers
+v0x7fa89ad16e20_0 .net "o_8", 0 0, L_0x7fa89ad17110;  1 drivers
+o0x7fa89aa32188 .functor BUFZ 1, C4<z>; HiZ drive
+v0x7fa89ad16ee0_0 .net "sys_clk", 0 0, o0x7fa89aa32188;  0 drivers
+o0x7fa89aa321b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0x7fa89ad16f80_0 .net "sys_rst", 0 0, o0x7fa89aa321b8;  0 drivers
+E_0x7fa89ad056c0/0 .event negedge, v0x7fa89ad16f80_0;
+E_0x7fa89ad056c0/1 .event posedge, v0x7fa89ad16ee0_0;
+E_0x7fa89ad056c0 .event/or E_0x7fa89ad056c0/0, E_0x7fa89ad056c0/1;
+L_0x7fa89ad17050 .arith/div 8, v0x7fa89ad16ad0_0, v0x7fa89ad16cf0_0;
+L_0x7fa89ad17110 .part L_0x7fa89ad17050, 0, 1;
+L_0x7fa89ad17210 .arith/div 16, v0x7fa89ad16980_0, v0x7fa89ad16ba0_0;
+L_0x7fa89ad172f0 .part L_0x7fa89ad17210, 0, 1;
+    .scope S_0x7fa89ad06690;
+T_0 ;
+    %pushi/vec4 1, 0, 8;
+    %store/vec4 v0x7fa89ad16ad0_0, 0, 8;
+    %pushi/vec4 1, 0, 8;
+    %store/vec4 v0x7fa89ad16cf0_0, 0, 8;
+    %pushi/vec4 1, 0, 16;
+    %store/vec4 v0x7fa89ad16980_0, 0, 16;
+    %pushi/vec4 1, 0, 16;
+    %store/vec4 v0x7fa89ad16ba0_0, 0, 16;
+    %end;
+    .thread T_0;
+    .scope S_0x7fa89ad06690;
+T_1 ;
+    %wait E_0x7fa89ad056c0;
+    %load/vec4 v0x7fa89ad16f80_0;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.0, 8;
+    %pushi/vec4 1, 0, 8;
+    %assign/vec4 v0x7fa89ad16ad0_0, 0;
+    %pushi/vec4 1, 0, 8;
+    %assign/vec4 v0x7fa89ad16cf0_0, 0;
+    %jmp T_1.1;
+T_1.0 ;
+    %load/vec4 v0x7fa89ad16ad0_0;
+    %addi 1, 0, 8;
+    %assign/vec4 v0x7fa89ad16ad0_0, 0;
+    %load/vec4 v0x7fa89ad16cf0_0;
+    %addi 1, 0, 8;
+    %assign/vec4 v0x7fa89ad16cf0_0, 0;
+T_1.1 ;
+    %jmp T_1;
+    .thread T_1;
+    .scope S_0x7fa89ad06690;
+T_2 ;
+    %wait E_0x7fa89ad056c0;
+    %load/vec4 v0x7fa89ad16f80_0;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_2.0, 8;
+    %pushi/vec4 1, 0, 16;
+    %assign/vec4 v0x7fa89ad16980_0, 0;
+    %pushi/vec4 1, 0, 16;
+    %assign/vec4 v0x7fa89ad16ba0_0, 0;
+    %jmp T_2.1;
+T_2.0 ;
+    %load/vec4 v0x7fa89ad16980_0;
+    %addi 1, 0, 16;
+    %assign/vec4 v0x7fa89ad16980_0, 0;
+    %load/vec4 v0x7fa89ad16ba0_0;
+    %addi 1, 0, 16;
+    %assign/vec4 v0x7fa89ad16ba0_0, 0;
+T_2.1 ;
+    %jmp T_2;
+    .thread T_2;
+# The file index is used to find the file name in the following table.
+:file_names 3;
+    "N/A";
+    "<interactive>";
+    "div.v";
diff --git a/compute/mul.v b/compute/mul.v
new file mode 100644
index 0000000..b9866e7
--- /dev/null
+++ b/compute/mul.v
@@ -0,0 +1,58 @@
+module mul(
+    (*mark_debug="true"*)input wire sys_clk,  // U18
+    (*mark_debug="true"*)input wire sys_rst  //J15
+);
+
+
+parameter t_1 = 8;
+(*mark_debug="true"*)reg [t_1-1:0] a_8 = 'b1;
+(*mark_debug="true"*)reg [t_1-1:0] b_8 = 'b1;
+(*mark_debug="true"*) wire o_8 = a_8 * b_8;
+
+always @(posedge sys_clk or  negedge sys_rst) begin
+    if (!sys_rst) begin
+        a_8 <= 'b1;
+        b_8 <= 'b1;
+    end
+    else begin
+        a_8 <= a_8 + 'b1;
+        b_8 <= b_8 + 'b1;
+    end
+end
+
+
+parameter t_2 = 16;
+(*mark_debug="true"*)reg [t_2-1:0] a_16 = 'b1;
+(*mark_debug="true"*)reg [t_2-1:0] b_16 = 'b1;
+(*mark_debug="true"*) wire o_18 = a_16 * b_16;
+
+always @(posedge sys_clk or  negedge sys_rst) begin
+    if (!sys_rst) begin
+        a_16 <= 'b1;
+        b_16 <= 'b1;
+    end
+    else begin
+        a_16 <= a_16 + 'b1;
+        b_16 <= b_16 + 'b1;
+    end
+end
+
+
+
+parameter t_3 = 28;
+(*mark_debug="true"*)reg [t_3-1:0] a_28 = 'b1_1000;
+(*mark_debug="true"*)reg [t_3-1:0] b_28 = 'b1;
+(*mark_debug="true"*) wire o_28 = a_28 * b_28;
+
+always @(posedge sys_clk or  negedge sys_rst) begin
+    if (!sys_rst) begin
+        a_28 <= 'b1;
+        b_28 <= 'b1;
+    end
+    else begin
+        a_28 <= a_28 + 'b1;
+        b_28 <= b_28 + 'b1;
+    end
+end
+
+endmodule
\ No newline at end of file
diff --git a/compute/mul.v.out b/compute/mul.v.out
new file mode 100755
index 0000000..07b0549
--- /dev/null
+++ b/compute/mul.v.out
@@ -0,0 +1,128 @@
+#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp
+:ivl_version "12.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi";
+:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi";
+S_0x7fc906406830 .scope module, "mul" "mul" 2 1;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "sys_clk";
+    .port_info 1 /INPUT 1 "sys_rst";
+P_0x7fc906406fb0 .param/l "t_1" 0 2 7, +C4<00000000000000000000000000001000>;
+P_0x7fc906406ff0 .param/l "t_2" 0 2 24, +C4<00000000000000000000000000010000>;
+P_0x7fc906407030 .param/l "t_3" 0 2 42, +C4<00000000000000000000000000011100>;
+v0x7fc906407770_0 .net *"_ivl_1", 7 0, L_0x7fc906418af0;  1 drivers
+v0x7fc906418030_0 .net *"_ivl_5", 15 0, L_0x7fc906418c70;  1 drivers
+v0x7fc9064180d0_0 .net *"_ivl_9", 27 0, L_0x7fc906418e50;  1 drivers
+v0x7fc906418180_0 .var "a_16", 15 0;
+v0x7fc9064182d0_0 .var "a_28", 27 0;
+v0x7fc906418420_0 .var "a_8", 7 0;
+v0x7fc9064184b0_0 .var "b_16", 15 0;
+v0x7fc906418560_0 .var "b_28", 27 0;
+v0x7fc906418630_0 .var "b_8", 7 0;
+v0x7fc906418770_0 .net "o_18", 0 0, L_0x7fc906418d70;  1 drivers
+v0x7fc906418800_0 .net "o_28", 0 0, L_0x7fc906418f40;  1 drivers
+v0x7fc9064188c0_0 .net "o_8", 0 0, L_0x7fc906418b90;  1 drivers
+o0x7fc906532248 .functor BUFZ 1, C4<z>; HiZ drive
+v0x7fc906418980_0 .net "sys_clk", 0 0, o0x7fc906532248;  0 drivers
+o0x7fc906532278 .functor BUFZ 1, C4<z>; HiZ drive
+v0x7fc906418a20_0 .net "sys_rst", 0 0, o0x7fc906532278;  0 drivers
+E_0x7fc906407670/0 .event negedge, v0x7fc906418a20_0;
+E_0x7fc906407670/1 .event posedge, v0x7fc906418980_0;
+E_0x7fc906407670 .event/or E_0x7fc906407670/0, E_0x7fc906407670/1;
+L_0x7fc906418af0 .arith/mult 8, v0x7fc906418420_0, v0x7fc906418630_0;
+L_0x7fc906418b90 .part L_0x7fc906418af0, 0, 1;
+L_0x7fc906418c70 .arith/mult 16, v0x7fc906418180_0, v0x7fc9064184b0_0;
+L_0x7fc906418d70 .part L_0x7fc906418c70, 0, 1;
+L_0x7fc906418e50 .arith/mult 28, v0x7fc9064182d0_0, v0x7fc906418560_0;
+L_0x7fc906418f40 .part L_0x7fc906418e50, 0, 1;
+    .scope S_0x7fc906406830;
+T_0 ;
+    %pushi/vec4 1, 0, 8;
+    %store/vec4 v0x7fc906418420_0, 0, 8;
+    %pushi/vec4 1, 0, 8;
+    %store/vec4 v0x7fc906418630_0, 0, 8;
+    %pushi/vec4 1, 0, 16;
+    %store/vec4 v0x7fc906418180_0, 0, 16;
+    %pushi/vec4 1, 0, 16;
+    %store/vec4 v0x7fc9064184b0_0, 0, 16;
+    %pushi/vec4 24, 0, 28;
+    %store/vec4 v0x7fc9064182d0_0, 0, 28;
+    %pushi/vec4 1, 0, 28;
+    %store/vec4 v0x7fc906418560_0, 0, 28;
+    %end;
+    .thread T_0;
+    .scope S_0x7fc906406830;
+T_1 ;
+    %wait E_0x7fc906407670;
+    %load/vec4 v0x7fc906418a20_0;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.0, 8;
+    %pushi/vec4 1, 0, 8;
+    %assign/vec4 v0x7fc906418420_0, 0;
+    %pushi/vec4 1, 0, 8;
+    %assign/vec4 v0x7fc906418630_0, 0;
+    %jmp T_1.1;
+T_1.0 ;
+    %load/vec4 v0x7fc906418420_0;
+    %addi 1, 0, 8;
+    %assign/vec4 v0x7fc906418420_0, 0;
+    %load/vec4 v0x7fc906418630_0;
+    %addi 1, 0, 8;
+    %assign/vec4 v0x7fc906418630_0, 0;
+T_1.1 ;
+    %jmp T_1;
+    .thread T_1;
+    .scope S_0x7fc906406830;
+T_2 ;
+    %wait E_0x7fc906407670;
+    %load/vec4 v0x7fc906418a20_0;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_2.0, 8;
+    %pushi/vec4 1, 0, 16;
+    %assign/vec4 v0x7fc906418180_0, 0;
+    %pushi/vec4 1, 0, 16;
+    %assign/vec4 v0x7fc9064184b0_0, 0;
+    %jmp T_2.1;
+T_2.0 ;
+    %load/vec4 v0x7fc906418180_0;
+    %addi 1, 0, 16;
+    %assign/vec4 v0x7fc906418180_0, 0;
+    %load/vec4 v0x7fc9064184b0_0;
+    %addi 1, 0, 16;
+    %assign/vec4 v0x7fc9064184b0_0, 0;
+T_2.1 ;
+    %jmp T_2;
+    .thread T_2;
+    .scope S_0x7fc906406830;
+T_3 ;
+    %wait E_0x7fc906407670;
+    %load/vec4 v0x7fc906418a20_0;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_3.0, 8;
+    %pushi/vec4 1, 0, 28;
+    %assign/vec4 v0x7fc9064182d0_0, 0;
+    %pushi/vec4 1, 0, 28;
+    %assign/vec4 v0x7fc906418560_0, 0;
+    %jmp T_3.1;
+T_3.0 ;
+    %load/vec4 v0x7fc9064182d0_0;
+    %addi 1, 0, 28;
+    %assign/vec4 v0x7fc9064182d0_0, 0;
+    %load/vec4 v0x7fc906418560_0;
+    %addi 1, 0, 28;
+    %assign/vec4 v0x7fc906418560_0, 0;
+T_3.1 ;
+    %jmp T_3;
+    .thread T_3;
+# The file index is used to find the file name in the following table.
+:file_names 3;
+    "N/A";
+    "<interactive>";
+    "mul.v";