yanguangshaonian
/
verilog_stu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
42 Commits
1 Branch
0 Tags
4.6 MiB
main
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '057f49b773'
${ noResults }
Commit Graph

2 Commits (057f49b7733b67f4bbd44c7ca5ac8ab3d2eacb22)

Author SHA1 Message Date
阳光少年 f0caf83860 始终仿真通过, 上板测试失败应该是不能采集整倍数的时钟 2 years ago
阳光少年 9a85504756 增加一个时钟倍频和分频的模块, 下班需要使用vivado仿真测试 2 years ago