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verilog_stu
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3 Commits (3816e69714ee2fd80b5c405356efa8ea57199cbf)

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阳光少年 3816e69714 优化代码, 防止发送过快或者晶振导致计数器误差, start_en在busy结束之前出现导致计数器不再工作 2 years ago
阳光少年 6ed71a9a79 仿真通过 2 years ago
阳光少年 2c713b8bff uart的接收模块完成 2 years ago