yanguangshaonian
/
verilog_stu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
39 Commits
1 Branch
0 Tags
4.6 MiB
main
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'f0caf83860'
${ noResults }
Commit Graph

2 Commits (f0caf83860730c264f0dc51804eff1e1612c4f99)

Author SHA1 Message Date
阳光少年 f0caf83860 始终仿真通过, 上板测试失败应该是不能采集整倍数的时钟 1 year ago
阳光少年 9a85504756 增加一个时钟倍频和分频的模块, 下班需要使用vivado仿真测试 1 year ago