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verilog_stu
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2 Commits (f5429a3e142727cbf3d7abdda590e3830924e1eb)

Author SHA1 Message Date
阳光少年 f0caf83860 始终仿真通过, 上板测试失败应该是不能采集整倍数的时钟 9 months ago
阳光少年 9a85504756 增加一个时钟倍频和分频的模块, 下班需要使用vivado仿真测试 9 months ago