module test_dt(
    input wire sys_clk,  // U18
    input wire sys_rst,  //J15
    output wire A, B, C, D, E, F, G, DP,
    output wire S1, S2, S3, S4
);


reg [25:0] CNT;

always @(posedge sys_clk or negedge sys_rst) begin
    if (sys_rst == 1'b0) begin
        CNT <= 25'd0;
    end
    else if (CNT < (25'd25000000 - 25'd1)) begin
        CNT <= CNT + 25'd1;
    end
    else begin
        CNT <= 25'b0;
    end
end



reg [7:0] data;
always @(posedge sys_clk or negedge sys_rst) begin
    if (sys_rst == 1'b0) begin 
        data <= 8'b1_00_0_0000;
    end
    else if (CNT == (25'd25000000 - 25'd1)) begin
        data[3:0] <= data[3:0] + 4'b1;
        data[6:5] <= data[6:5] + 2'b1;
    end
    else begin

    end
end


dt u_dt(
    .data (data),
    .A (A),
    .B (B),
    .C (C),
    .D (D),
    .E (E),
    .F (F),
    .G (G),
    .DP (DP),
    .S1 (S1),
    .S2 (S2),
    .S3 (S3),
    .S4 (S4)
);

endmodule