// 在verilog中直接使用 / 进行除法运算, 位数越多, 消耗的资源会非常多, 而且时序 无法控制
module div(
    (*mark_debug="true"*)input wire sys_clk,  // U18
    (*mark_debug="true"*)input wire sys_rst  //J15
);


parameter t_1 = 8;
(*mark_debug="true"*)reg [t_1-1:0] a_8 = 'b1;
(*mark_debug="true"*)reg [t_1-1:0] b_8 = 'b1;
(*mark_debug="true"*) wire o_8 = a_8 / b_8;

always @(posedge sys_clk or  negedge sys_rst) begin
    if (!sys_rst) begin
        a_8 <= 'b1;
        b_8 <= 'b1;
    end
    else begin
        a_8 <= a_8 + 'b1;
        b_8 <= b_8 + 'b1;
    end
end


parameter t_2 = 16;
(*mark_debug="true"*)reg [t_2-1:0] a_16 = 'b1;
(*mark_debug="true"*)reg [t_2-1:0] b_16 = 'b1;
(*mark_debug="true"*) wire o_18 = a_16 / b_16;

always @(posedge sys_clk or  negedge sys_rst) begin
    if (!sys_rst) begin
        a_16 <= 'b1;
        b_16 <= 'b1;
    end
    else begin
        a_16 <= a_16 + 'b1;
        b_16 <= b_16 + 'b1;
    end
end



parameter t_3 = 28;
(*mark_debug="true"*)reg [t_3-1:0] a_28 = 'b1_1000;
(*mark_debug="true"*)reg [t_3-1:0] b_28 = 'b1;
(*mark_debug="true"*) wire o_28 = a_28 / b_28;

always @(posedge sys_clk or  negedge sys_rst) begin
    if (!sys_rst) begin
        a_28 <= 'b1;
        b_28 <= 'b1;
    end
    else begin
        a_28 <= a_28 + 'b1;
        b_28 <= b_28 + 'b1;
    end
end

endmodule