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35 lines
916 B
Verilog
35 lines
916 B
Verilog
module decoder38(
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input wire [2:0]i,
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output wire [7:0]o
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);
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// 直接使用门电路连线
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wire [7:0] w_o;
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assign w_o[0] = i[0] && i[1] && i[2];
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assign w_o[1] = !i[0] && i[1] && i[2];
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assign w_o[2] = i[0] && !i[1] && i[2];
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assign w_o[3] = !i[0] && !i[1] && i[2];
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assign w_o[4] = i[0] && i[1] && !i[2];
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assign w_o[5] = !i[0] && i[1] && !i[2];
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assign w_o[6] = i[0] && !i[1] && !i[2];
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assign w_o[7] = !i[0] && !i[1] && !i[2];
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assign o = w_o;
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// 使用 always 连线
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reg [7:0]r_o;
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always @(i) begin
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// 阻塞赋值
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r_o[0] = i[0] && i[1] && i[2];
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r_o[1] = !i[0] && i[1] && i[2];
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r_o[2] = i[0] && !i[1] && i[2];
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r_o[3] = !i[0] && !i[1] && i[2];
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// 非阻塞赋值, 他们是并行连线的
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r_o[4] <= i[0] && i[1] && !i[2];
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r_o[5] <= !i[0] && i[1] && !i[2];
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r_o[6] <= i == 3'b001; // i[0] && !i[1] && !i[2];
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r_o[7] <= !i[0] && !i[1] && !i[2];
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end
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assign o=r_o;
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endmodule |