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58 lines
1.2 KiB
Verilog
58 lines
1.2 KiB
Verilog
module mul(
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(*mark_debug="true"*)input wire sys_clk, // U18
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(*mark_debug="true"*)input wire sys_rst //J15
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);
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parameter t_1 = 8;
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(*mark_debug="true"*)reg [t_1-1:0] a_8 = 'b1;
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(*mark_debug="true"*)reg [t_1-1:0] b_8 = 'b1;
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(*mark_debug="true"*) wire o_8 = a_8 * b_8;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (!sys_rst) begin
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a_8 <= 'b1;
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b_8 <= 'b1;
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end
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else begin
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a_8 <= a_8 + 'b1;
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b_8 <= b_8 + 'b1;
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end
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end
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parameter t_2 = 16;
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(*mark_debug="true"*)reg [t_2-1:0] a_16 = 'b1;
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(*mark_debug="true"*)reg [t_2-1:0] b_16 = 'b1;
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(*mark_debug="true"*) wire o_18 = a_16 * b_16;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (!sys_rst) begin
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a_16 <= 'b1;
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b_16 <= 'b1;
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end
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else begin
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a_16 <= a_16 + 'b1;
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b_16 <= b_16 + 'b1;
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end
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end
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parameter t_3 = 28;
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(*mark_debug="true"*)reg [t_3-1:0] a_28 = 'b1_1000;
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(*mark_debug="true"*)reg [t_3-1:0] b_28 = 'b1;
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(*mark_debug="true"*) wire o_28 = a_28 * b_28;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (!sys_rst) begin
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a_28 <= 'b1;
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b_28 <= 'b1;
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end
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else begin
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a_28 <= a_28 + 'b1;
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b_28 <= b_28 + 'b1;
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end
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end
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endmodule |