You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
61 lines
1.9 KiB
Verilog
61 lines
1.9 KiB
Verilog
// f20 f19 b20 c20 j16 k16 m18 m17 l17 l16 l15 l14 m15 m14
|
|
// 7 8 9 10 11 12 6 5 4 3 2 1
|
|
// B S3 S2 F A S1 S4 G C DP D E
|
|
module dt(
|
|
input wire [7:0]data, // en: 1, select:2, dp: 1, data: 4
|
|
output reg A, B, C, D, E, F, G, DP,
|
|
output reg S1, S2, S3, S4
|
|
);
|
|
|
|
|
|
// ABCDEFG
|
|
parameter _SHOW_0 = 8'B1111110;
|
|
parameter _SHOW_1 = 8'B0110000;
|
|
parameter _SHOW_2 = 8'B1101101;
|
|
parameter _SHOW_3 = 8'B1111001;
|
|
parameter _SHOW_4 = 8'B0110011;
|
|
parameter _SHOW_5 = 8'B1011011;
|
|
parameter _SHOW_6 = 8'B1011111;
|
|
parameter _SHOW_7 = 8'B1110000;
|
|
parameter _SHOW_8 = 8'B1111111;
|
|
parameter _SHOW_9 = 8'B1110011;
|
|
parameter _SHOW_A = 8'B1110111;
|
|
parameter _SHOW_B = 8'B0011111;
|
|
parameter _SHOW_C = 8'B1001110;
|
|
parameter _SHOW_D = 8'B0111101;
|
|
parameter _SHOW_E = 8'B1001111;
|
|
parameter _SHOW_F = 8'B1000111;
|
|
|
|
|
|
always @(data) begin
|
|
DP = data[4];
|
|
|
|
case (data[3:0])
|
|
4'b0000: {A, B, C, D, E, F, G} = _SHOW_0;
|
|
4'b0001: {A, B, C, D, E, F, G} = _SHOW_1;
|
|
4'b0010: {A, B, C, D, E, F, G} = _SHOW_2;
|
|
4'b0011: {A, B, C, D, E, F, G} = _SHOW_3;
|
|
4'b0100: {A, B, C, D, E, F, G} = _SHOW_4;
|
|
4'b0101: {A, B, C, D, E, F, G} = _SHOW_5;
|
|
4'b0110: {A, B, C, D, E, F, G} = _SHOW_6;
|
|
4'b0111: {A, B, C, D, E, F, G} = _SHOW_7;
|
|
4'b1000: {A, B, C, D, E, F, G} = _SHOW_8;
|
|
4'b1001: {A, B, C, D, E, F, G} = _SHOW_9;
|
|
4'b1010: {A, B, C, D, E, F, G} = _SHOW_A;
|
|
4'b1011: {A, B, C, D, E, F, G} = _SHOW_B;
|
|
4'b1100: {A, B, C, D, E, F, G} = _SHOW_C;
|
|
4'b1101: {A, B, C, D, E, F, G} = _SHOW_D;
|
|
4'b1110: {A, B, C, D, E, F, G} = _SHOW_E;
|
|
4'b1111: {A, B, C, D, E, F, G} = _SHOW_F;
|
|
default: ;
|
|
endcase
|
|
|
|
if (data[7]) begin
|
|
{S4, S3, S2, S1} = ~(4'b0001 << data[6:5]);
|
|
end
|
|
else begin
|
|
{S4, S3, S2, S1} = 4'b1111;
|
|
end
|
|
|
|
end
|
|
endmodule |