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72 lines
1.3 KiB
Verilog
72 lines
1.3 KiB
Verilog
`timescale 1ns/1ns
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module tb_dt();
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// 我们如果上板验证, 需要再 .xdc文件中, 添加时钟约束
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// create_clock -period 20.000 -name sys_clk [get_ports sys_clk]
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// 创建一个时钟, 周期是20纳秒, 对应的端口是系统时钟
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reg sys_clk;
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reg sys_rst;
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initial begin
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sys_clk <= 1'b0;
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// 复位
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sys_rst <= 1'b0;
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#200
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// 结束复位
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sys_rst <= 1'b1;
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end
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// 每20ns 产生一个时钟周期, 所以需要10ns 翻转一次
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always #10 sys_clk = ~sys_clk;
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reg [5:0] CNT;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (sys_rst == 1'b0) begin
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CNT <= 5'd0;
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end
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else if (CNT < (5'd25 - 5'd1)) begin
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CNT <= CNT + 5'd1;
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end
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else begin
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CNT <= 5'b0;
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end
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end
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reg [7:0] data;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (sys_rst == 1'b0) begin
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data <= 8'b1_00_0_0000;
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end
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else if (CNT == (5'd25 - 5'd1)) begin
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data[3:0] <= data[3:0] + 4'b1;
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data[6:5] <= data[6:5] + 2'b1;
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end
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else begin
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end
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end
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wire [7:0] D;
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wire [3:0] S;
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dt u_dt(
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.data (data),
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.A (D[0]),
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.B (D[1]),
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.C (D[2]),
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.D (D[3]),
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.E (D[4]),
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.F (D[5]),
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.G (D[6]),
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.DP (D[7]),
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.S1 (S[0]),
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.S2 (S[1]),
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.S3 (S[2]),
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.S4 (S[3])
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);
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endmodule |