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56 lines
920 B
Verilog
56 lines
920 B
Verilog
module test_dt(
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input wire sys_clk, // U18
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input wire sys_rst, //J15
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output wire A, B, C, D, E, F, G, DP,
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output wire S1, S2, S3, S4
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);
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reg [25:0] CNT;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (sys_rst == 1'b0) begin
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CNT <= 25'd0;
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end
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else if (CNT < (25'd25000000 - 25'd1)) begin
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CNT <= CNT + 25'd1;
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end
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else begin
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CNT <= 25'b0;
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end
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end
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reg [7:0] data;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (sys_rst == 1'b0) begin
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data <= 8'b1_00_0_0000;
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end
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else if (CNT == (25'd25000000 - 25'd1)) begin
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data[3:0] <= data[3:0] + 4'b1;
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data[6:5] <= data[6:5] + 2'b1;
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end
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else begin
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end
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end
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dt u_dt(
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.data (data),
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.A (A),
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.B (B),
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.C (C),
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.D (D),
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.E (E),
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.F (F),
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.G (G),
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.DP (DP),
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.S1 (S1),
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.S2 (S2),
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.S3 (S3),
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.S4 (S4)
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);
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endmodule |