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`timescale 1ns/1ns
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module tb_ram();
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reg sys_clk;
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reg sys_rst;
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always #10 sys_clk = ~sys_clk;
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initial begin
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sys_clk <= 1'b0;
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sys_rst <= 1'b0;
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#50
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sys_rst <= 1'b1;
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end
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ram u_ram(
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.sys_clk(sys_clk),
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.sys_rst(sys_rst)
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);
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endmodule |