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119 lines
2.5 KiB
Verilog
119 lines
2.5 KiB
Verilog
// 呼吸灯实验
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`timescale 1ns/1ns
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module tb_bln();
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reg sys_clk;
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reg sys_rst;
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always #10 sys_clk = ~sys_clk;
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// parameter ns_max = 10'b110_0100; // 100次
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// parameter us_max = 10'b11_1110_1000; // 1000次
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// parameter ms_max = 10'b11_1110_1000; // 1000次
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parameter ns_max = 10'b110_0100 >> 3; // 12
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parameter us_max = 10'b11_1110_1000 >> 6; // 15
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parameter ms_max = 10'b11_1110_1000 >> 6; // 15
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initial begin
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sys_clk <= 1'b0;
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sys_rst <= 1'b0;
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sys_rst <= 1'b1;
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end
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reg [9:0] ns_cnt;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (sys_rst == 1'b0) begin
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ns_cnt <= 10'b0;
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end
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// 到了2us整 (每个时钟周期20ns, 当前已经100个20ns了 清零吧)
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else if (ns_cnt == ns_max - 10'b1) begin
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ns_cnt <= 10'b0;
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end
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else begin
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ns_cnt <= ns_cnt + 10'b1;
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end
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end
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reg [9:0] us_cnt;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (sys_rst == 1'b0) begin
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us_cnt <= 10'b0;
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end
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// 到了2ms整
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else if ((us_cnt == us_max - 10'b1) && (ns_cnt == ns_max - 10'b1)) begin
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us_cnt <= 10'b0;
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end
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// 到了2us整
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else if (ns_cnt == ns_max - 10'b1) begin
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us_cnt <= us_cnt + 10'b1;
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end
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else begin
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us_cnt <= us_cnt;
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end
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end
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reg [9:0] ms_cnt;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (sys_rst == 1'b0) begin
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ms_cnt <= 10'b0;
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end
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// 到了2s整 清零
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else if ((ms_cnt == ms_max - 10'b1) && (us_cnt == us_max - 10'b1) && (ns_cnt == ns_max - 10'b1)) begin
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ms_cnt <= 10'b0;
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end
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// 到了2ms整
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else if ((us_cnt == us_max - 10'b1) && (ns_cnt == ns_max - 10'b1)) begin
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ms_cnt <= ms_cnt + 10'b1;
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end
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else begin
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ms_cnt <= ms_cnt;
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end
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end
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reg flag; // 2s切换一下状态
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always @(posedge sys_clk or negedge sys_rst) begin
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if (sys_rst == 1'b0) begin
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flag <= 1'b0;
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end
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else if ((ms_cnt == ms_max - 10'b1) && (us_cnt == us_max - 10'b1) && (ns_cnt == ns_max - 10'b1)) begin
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flag <= !flag;
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end
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else begin
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flag <= flag;
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end
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end
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reg [7:0]x;
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reg [7:0]y;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (sys_rst == 1'b0) begin
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x <= 8'b0000_0000;
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y <= 8'b1111_1111;
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end
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else begin
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end
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case({flag, us_cnt <= ms_cnt})
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2'b01: x <= 8'b0000_0001;
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2'b00: x <= 8'b0000_0000;
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2'b11: x <= 8'b0000_0000;
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2'b10: x <= 8'b0000_0001;
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default ;
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endcase
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end
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endmodule
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