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module key_1(
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input wire sys_clk, // U18
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input wire sys_rst, //J15
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// d20,d19,b19,a20
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output reg c4, c3, c2, c1,
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// f16,f17,e18,e19
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output reg r4, r3, r2, r1,
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// f20 f19 b20 c20 j16 k16 m18 m17 l17 l16 l15 l14 m15 m14 n16 n15
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// x4 x2 x1 x3 x6 x7 x5 x8
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// y2 y3 y5 y8 y7 y1 y6 y4
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output wire o1, o2, o3, o4, o5, o6, o7, o8, o16,o15,o14,o13,o12,o11,o10,o9
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);
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reg [7:0] KEY_CODE;
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parameter GET_START = 4'b0001 << 0;
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parameter GET_ROW = 4'b0001 << 1;
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parameter GET_COL = 4'b0001 << 2;
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parameter GET_END = 4'b0001 << 3;
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reg STATUS = 4'b0000;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (sys_rst == 1'b0) begin
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STATUS <= GET_START;
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end
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else begin
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end
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end
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// 每个时钟周期<E591A8>?查行
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always @(posedge sys_clk or negedge sys_rst) begin
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// todo <20>?查锁
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// todo 可能会一次按多个按键, 后面再处理吧
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if (STATUS == GET_START) begin
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STATUS <= GET_ROW;
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{c4, c3, c2, c1} <= 4'b1111;
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{r4, r3, r2, r1} <= 4'b0000;
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KEY_CODE <= 8'b00000000;
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end
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else if (STATUS == GET_ROW && {c4, c3, c2, c1} != 4'b1111) begin
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KEY_CODE[7:4] <= {c4, c3, c2, c1};
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STATUS <= GET_COL;
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{c4, c3, c2, c1} <= 4'b0000;
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{r4, r3, r2, r1} <= 4'b1111;
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end
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else if (STATUS == GET_COL && {r4, r3, r2, r1} != 4'b1111) begin
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KEY_CODE[3:0] <= {r4, r3, r2, r1};
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STATUS <= GET_END;
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end
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else if (STATUS == GET_END) begin
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STATUS <= GET_START;
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end
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else begin
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end
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end
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reg [7:0] x;
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reg [7:0] y;
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always @(posedge sys_clk or negedge sys_rst) begin
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if (sys_rst == 1'b0) begin
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x <= 8'b0000_0000;
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y <= 8'b1111_1111;
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end
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else begin
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x <= KEY_CODE;
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end
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end
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lm u_lm(
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.x (x),
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.y (y),
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.o1 (o1),
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.o2 (o2),
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.o3 (o3),
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.o4 (o4),
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.o5 (o5),
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.o6 (o6),
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.o7 (o7),
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.o8 (o8),
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.o9 (o9),
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.o10 (o10),
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.o11 (o11),
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.o12 (o12),
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.o13 (o13),
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.o14 (o14),
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.o15 (o15),
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.o16 (o16)
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);
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endmodule |