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16 lines
570 B
Verilog
16 lines
570 B
Verilog
module lm(
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input wire [7:0] x,
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input wire [7:0] y,
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// f20 f19 b20 c20 j16 k16 m18 m17 l17 l16 l15 l14 m15 m14 n16 n15
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// x4 x2 x1 x3 x6 x7 x5 x8
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// y2 y3 y5 y8 y7 y1 y6 y4
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output wire o1, o2, o3, o4, o5, o6, o7, o8, o16,o15,o14,o13,o12,o11,o10,o9
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);
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// wire [7:0] x = 8'b1111_1111;
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// wire [7:0] y = 8'b1111_1111;
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assign {o9, o14, o8, o12, o1, o7, o2, o5} = x;
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assign {o16, o15, o11, o6, o10, o4, o3, o13} = ~y;
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endmodule |