verilog_stu/led_matrix/tb_lm_1.v

`timescale 1ns/1ns

module tb_lm();

reg k_1;
reg k_2;

reg flag;  // 状态改变周期 现在500ns改变一次状态

reg sys_clk;
reg sys_rst;


always #10 sys_clk = ~sys_clk;

initial begin
    sys_clk <= 1'b0;
    sys_rst <= 1'b0;
    #200
    sys_rst <= 1'b1;

    {k_2, k_1} <= 2'b10;

    #4000
    {k_2, k_1} <= 2'b01;

    #4000
    {k_2, k_1} <= 2'b00;
end


reg [5:0] CNT;
always @(posedge sys_clk or negedge sys_rst) begin
    if (sys_rst == 1'b0) begin
        CNT <= 5'd0;
    end
    else if (CNT < (5'd25 - 5'd1)) begin
        CNT <= CNT + 5'd1;
    end
    else begin
        CNT <= 5'b0;
    end
end


reg [7:0]x;
reg [7:0]y;
always @(posedge sys_clk or negedge sys_rst) begin
    if (sys_rst == 1'b0) begin
        {k_2, k_1} <= 2'b11;
        x <= 8'b00000000;
        y <= 8'b11111111;  // 所有的都显示算了
    end
    else if ({k_2, k_1} == 2'b10) begin
        case (flag)
            1'b0: x <= 8'b1010_1010;
            1'b1: x <= 8'b0101_0101;
        endcase
    end
    else if ({k_2, k_1} == 2'b01) begin
        case (flag)
            1'b0: x <= 8'b1111_0000;
            1'b1: x <= 8'b0000_1111;
        endcase
    end
    else begin
        x <= 8'b00000000;
    end
end

always @(posedge sys_clk or negedge sys_rst) begin
    if (sys_rst == 1'b0) begin
        flag <= 1'b0;
    end
    else if (CNT == (5'd25 - 5'd1)) begin
        flag <= !flag;
    end
    else begin
    end
end


lm u_lm(
    .x (x),
    .y (y)
);


endmodule