verilog_stu/led_matrix/test.v

module test_lm(
    input wire sys_clk,  // U18
    input wire sys_rst,  //J15
    output wire o1, o2, o3, o4, o5, o6, o7, o8, o16,o15,o14,o13,o12,o11,o10,o9
);

reg [2:0]Y_IDX = 3'b000;  // 逐行显示, 当前第几行了, 一共8行


reg [25:0] CNT;

always @(posedge sys_clk or negedge sys_rst) begin
    if (sys_rst == 1'b0) begin
        CNT <= 25'd0;
    end
    else if (CNT < (25'd25000000 - 25'd1)) begin
        CNT <= CNT + 25'd1;
    end
    else begin
        CNT <= 25'b0;
    end
end

parameter show_data = 64'b10000000_01000000_00100000_00010000_00001000_00000100_00000010_00000001;


reg [7:0]x = 8'b1010_1100;

always @(posedge sys_clk or negedge sys_rst) begin
    if (sys_rst == 1'b0) begin
        x <= 8'b0000_0000;  //不通电了
    end
    else if (CNT == (25'd25000000 - 25'd1)) begin
        // 推进状态, 选择一行x
        x <= show_data[(Y_IDX * 8)+:8];
    end
    else begin
    end
end




reg [7:0]y = 8'b1111_1111;
always @(posedge sys_clk or negedge sys_rst) begin
    if (sys_rst == 1'b0) begin
        y <= 8'b1111_1111;  // x已经变成0了, 这里防止二极管接反, 就继续片选即可 内部低电平
        Y_IDX <= 3'b000;
    end
    else if (CNT == (25'd25000000 - 25'd1)) begin
        // 推进状态
        case (&y)
            1'b1: y <= 8'b0000_0001;
            default y <= {y[6:0], y[7]};
        endcase
        Y_IDX <= Y_IDX + 3'b1;
    end
    else begin
    end
end



lm u_lm(
    .x (x),
    .y (y),
    .o1 (o1),
    .o2 (o2),
    .o3 (o3),
    .o4 (o4),
    .o5 (o5),
    .o6 (o6),
    .o7 (o7),
    .o8 (o8),
    .o9 (o9),
    .o10 (o10),
    .o11 (o11),
    .o12 (o12),
    .o13 (o13),
    .o14 (o14),
    .o15 (o15),
    .o16 (o16)
);


endmodule