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verilog_stu
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SystemVerilog 67.9%
Verilog 22%
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阳光少年 1aad27244b 修改变量名 10 months ago
.vscode 增加一下项目文件 10 months ago
38decoder 仓库整理 10 months ago
dip 修改变量名 10 months ago
led 仓库文件整理 10 months ago
README.md Initial commit 10 months ago

README.md

verilog_stu