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verilog_stu
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SystemVerilog 67.9%
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阳光少年 5727b34d35 增加一下项目文件 10 months ago
.vscode 增加一下项目文件 10 months ago
38decoder.v 38译码器和led完成 10 months ago
38decoder.v.out 38译码器和led完成 10 months ago
README.md Initial commit 10 months ago
led.v 38译码器和led完成 10 months ago
led.v.out 38译码器和led完成 10 months ago

README.md

verilog_stu