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32 lines
819 B
Verilog
32 lines
819 B
Verilog
// 对时钟信号使用ip核进行分频倍频和偏移
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module clk_wiz(
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(*mark_debug="true"*)input wire sys_clk, // U18
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(*mark_debug="true"*)input wire sys_rst, //J15
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(*mark_debug="true"*)output wire clk_100m,
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(*mark_debug="true"*)output wire clk_100m_r, // 180度
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(*mark_debug="true"*)output wire clk_50m,
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(*mark_debug="true"*)output wire clk_25m
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);
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wire locked; // 内部时钟是否稳定
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wire rst;
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// 如果时钟信号稳定之后, 且sys是高电平, 表示板子已经可以正常使用了
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// 其他的例化可以使用该信号 当做是否复位标志
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assign global_rst = locked && sys_rst;
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clk_wiz_0 u_clk_wiz_0(
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.clk_in1(sys_clk),
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.reset(!sys_rst),
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.clk_out1(clk_100m),
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.clk_out2(clk_100m_r),
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.clk_out3(clk_50m),
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.clk_out4(clk_25m)
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);
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endmodule |