You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
74 lines
1.7 KiB
Verilog
74 lines
1.7 KiB
Verilog
`timescale 1ns/1ns
|
|
module tb_ram();
|
|
|
|
reg sys_clk;
|
|
reg sys_rst;
|
|
always #10 sys_clk = ~sys_clk;
|
|
|
|
|
|
initial begin
|
|
sys_clk <= 1'b0;
|
|
sys_rst <= 1'b0;
|
|
#50
|
|
sys_rst <= 1'b1;
|
|
end
|
|
|
|
reg ram_en;
|
|
always @(posedge sys_clk or negedge sys_rst) begin
|
|
if (!sys_rst) begin
|
|
ram_en <= 1'b0;
|
|
end
|
|
// 只有在复位之后, 才允许启动ram
|
|
else begin
|
|
ram_en <= 1'b1;
|
|
end
|
|
end
|
|
|
|
|
|
reg [7:0]counter; // 计数到15 清零, 变化范围 0~15
|
|
wire ram_rw;
|
|
assign ram_rw = ram_en && (counter <= 8'b111); // 计数器 分成读写各占一半时间, 0~7的时候高电平进行写, 8~15低电平进行读取
|
|
always @(posedge sys_clk or negedge sys_rst) begin
|
|
if (!sys_rst) begin
|
|
counter <= 8'b0;
|
|
end
|
|
// 没有启用ram禁止计数
|
|
else if (ram_en == 1'b0 || counter == 8'b1111) begin
|
|
counter <= 8'b0;
|
|
end
|
|
else begin
|
|
counter <= counter + 8'b1;
|
|
end
|
|
end
|
|
|
|
reg [2:0]ram_data; // 假想写入的数据, 数据变化范围是0~7, 只有在 ram_rw 是写入的时候进行累加并写入地址内
|
|
always @(posedge sys_clk or negedge sys_rst) begin
|
|
if (!sys_rst) begin
|
|
ram_data <= 3'b0;
|
|
end
|
|
// 如果是写, 并且还没到最大数
|
|
else if (ram_rw && ram_data < 3'b111) begin
|
|
ram_data <= ram_data + 3'b1;
|
|
end
|
|
else begin
|
|
ram_data <= 3'b0;
|
|
end
|
|
end
|
|
|
|
|
|
reg [2:0]ram_addr; // 地址变化范围 0~7就行了
|
|
always @(posedge sys_clk or negedge sys_rst) begin
|
|
if (!sys_rst) begin
|
|
ram_addr <= 3'b0;
|
|
end
|
|
else if (ram_en && ram_addr < 3'b111) begin
|
|
ram_addr <= ram_addr + 3'b1;
|
|
end
|
|
else begin
|
|
ram_addr <= 3'b0;
|
|
end
|
|
end
|
|
|
|
|
|
|
|
endmodule |