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26 lines
548 B
Verilog
26 lines
548 B
Verilog
module td_led ();
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`timescale 1ns/1ns // 睡眠的 单位/精度
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reg td_key; // 定义内内部的信号 设置为寄存器类型(按键是在 initial 语句中赋值, 以使用寄存器类型)
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wire td_led; // 定义内部的输出信号, 使用 wire 类型
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// 信号初始化的设置
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initial begin
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td_key <= 1'b1; // 不阻塞的设置内部初始值
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#200; // 阻塞 200ns
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td_key <= 1'b0;
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#500;
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td_key <= 1'b1;
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#1000;
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td_key <= 1'b0;
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end
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// 例化
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led u_led(
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.key (td_key),
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.led (td_led)
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);
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endmodule |