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verilog_stu
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SystemVerilog 67.9%
Verilog 22%
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阳光少年 e24c464e78 38译码器和led完成 12 months ago
38decoder.v 38译码器和led完成 12 months ago
38decoder.v.out 38译码器和led完成 12 months ago
README.md Initial commit 12 months ago
led.v 38译码器和led完成 12 months ago
led.v.out 38译码器和led完成 12 months ago

README.md

verilog_stu