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@ -1,5 +1,3 @@
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// https://github.com/ufrisk/pcileech/blob/master/pcileech/device.c
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use std::ffi::c_void;
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use std::os::raw::c_char;
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use std::path::Path;
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@ -9,17 +7,23 @@ use std::sync::{Arc, Mutex};
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use log::{error, info};
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use memflow::*;
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use memflow_derive::connector;
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use memflow::cglue;
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use memflow::mem::phys_mem::*;
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use memflow::prelude::v1::*;
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use leechcore_sys::*;
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const PAGE_SIZE: usize = 0x1000usize;
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const BUF_ALIGN: u64 = 4;
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// the absolute minimum BUF_ALIGN is 4.
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// using 8 bytes as BUF_ALIGN here simplifies things a lot
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// and makes our gap detection code work in cases where page boundaries would be crossed.
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const BUF_ALIGN: u64 = 8;
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const BUF_MIN_LEN: usize = 8;
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const BUF_LEN_ALIGN: usize = 8;
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cglue_impl_group!(PciLeech, ConnectorInstance<'a>, {});
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fn build_lc_config(device: &str) -> LC_CONFIG {
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let cdevice = unsafe { &*(device.as_bytes() as *const [u8] as *const [c_char]) };
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let mut adevice: [c_char; 260] = [0; 260];
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@ -47,43 +51,34 @@ const fn calc_num_pages(start: u64, size: u64) -> u64 {
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}
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#[allow(clippy::mutex_atomic)]
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#[derive(Debug)]
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#[derive(Clone)]
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pub struct PciLeech {
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handle: Arc<Mutex<HANDLE>>,
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metadata: PhysicalMemoryMetadata,
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mem_map: MemoryMap<(Address, usize)>,
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conf: LC_CONFIG,
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mem_map: Option<MemoryMap<(Address, umem)>>,
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}
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unsafe impl Send for PciLeech {}
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impl Clone for PciLeech {
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fn clone(&self) -> Self {
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Self {
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handle: self.handle.clone(),
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metadata: self.metadata,
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mem_map: self.mem_map.clone(),
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}
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}
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}
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// TODO: proper drop + free impl -> LcMemFree(pLcErrorInfo);
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#[allow(clippy::mutex_atomic)]
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impl PciLeech {
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pub fn new(device: &str) -> Result<Self> {
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Self::with_mapping(device, MemoryMap::new())
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Self::new_internal(device, None)
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}
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pub fn with_memmap<P: AsRef<Path>>(device: &str, path: P) -> Result<Self> {
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pub fn with_mem_map_file<P: AsRef<Path>>(device: &str, path: P) -> Result<Self> {
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info!(
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"loading memory mappings from file: {}",
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path.as_ref().to_string_lossy()
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);
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let memmap = MemoryMap::open(path)?;
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info!("{:?}", memmap);
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Self::with_mapping(device, memmap)
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let mem_map = MemoryMap::open(path)?;
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info!("{:?}", mem_map);
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Self::new_internal(device, Some(mem_map))
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}
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#[allow(clippy::mutex_atomic)]
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fn with_mapping(device: &str, mem_map: MemoryMap<(Address, usize)>) -> Result<Self> {
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fn new_internal(device: &str, mem_map: Option<MemoryMap<(Address, umem)>>) -> Result<Self> {
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// open device
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let mut conf = build_lc_config(device);
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let err = std::ptr::null_mut::<PLC_CONFIG_ERRORINFO>();
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@ -91,17 +86,13 @@ impl PciLeech {
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if handle.is_null() {
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// TODO: handle version error
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// TODO: handle special case of fUserInputRequest
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error!("leechcore error: {:?}", err);
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return Err(Error::Connector("unable to create leechcore context"));
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return Err(Error(ErrorOrigin::Connector, ErrorKind::Configuration)
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.log_error(&format!("unable to create leechcore context: {:?}", err)));
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}
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Ok(Self {
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handle: Arc::new(Mutex::new(handle)),
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metadata: PhysicalMemoryMetadata {
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size: conf.paMax as usize,
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readonly: conf.fVolatile == 0,
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// TODO: writable flag
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},
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conf,
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mem_map,
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})
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}
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@ -124,14 +115,25 @@ struct WriteGap {
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in_end: usize,
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}
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// TODO: handle mem_map
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impl PhysicalMemory for PciLeech {
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fn phys_read_raw_list(&mut self, data: &mut [PhysicalReadData]) -> Result<()> {
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//let mem_map = &self.mem_map;
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fn phys_read_raw_iter<'a>(
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&mut self,
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data: CIterator<PhysicalReadData<'a>>,
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out_fail: &mut ReadFailCallback<'_, 'a>,
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) -> Result<()> {
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let vec = if let Some(mem_map) = &self.mem_map {
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mem_map
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.map_iter(data, out_fail)
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.map(|d| (d.0 .0.into(), d.1))
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.collect::<Vec<_>>()
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} else {
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data.map(|MemData(addr, buf)| (addr, buf))
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.collect::<Vec<_>>()
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};
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// get total number of pages
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let num_pages = data.iter().fold(0u64, |acc, read| {
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acc + calc_num_pages(read.0.as_u64(), read.1.len() as u64)
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let num_pages = vec.iter().fold(0u64, |acc, read| {
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acc + calc_num_pages(read.0.to_umem(), read.1.len() as u64)
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});
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// allocate scatter buffer
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@ -145,28 +147,45 @@ impl PhysicalMemory for PciLeech {
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)
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};
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if result != 1 {
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return Err(Error::Connector("unable to allocate scatter buffer"));
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return Err(Error(ErrorOrigin::Connector, ErrorKind::InvalidMemorySize)
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.log_error("unable to allocate scatter buffer"));
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}
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// prepare mems
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let mut gaps = Vec::new();
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let mut i = 0usize;
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for read in data.iter_mut() {
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for read in vec.into_iter() {
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for (page_addr, out) in read.1.page_chunks(read.0.into(), PAGE_SIZE) {
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let mem = unsafe { *mems.add(i) };
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let addr_align = page_addr.as_u64() & (BUF_ALIGN - 1);
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let addr_align = page_addr.to_umem() & (BUF_ALIGN - 1);
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let len_align = out.len() & (BUF_LEN_ALIGN - 1);
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if addr_align == 0 && len_align == 0 && out.len() >= BUF_MIN_LEN {
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// properly aligned read
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unsafe { (*mem).qwA = page_addr.as_u64() };
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unsafe { (*mem).pb = out.as_mut_ptr() };
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unsafe { (*mem).qwA = page_addr.to_umem() };
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unsafe { (*mem).__bindgen_anon_1.pb = out.as_mut_ptr() };
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unsafe { (*mem).cb = out.len() as u32 };
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} else {
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// non-aligned or small read
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let mut buffer_len = (out.len() + addr_align as usize).max(BUF_MIN_LEN);
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buffer_len += BUF_LEN_ALIGN - (buffer_len & (BUF_LEN_ALIGN - 1));
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let page_addr_align = page_addr.to_umem() - addr_align;
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let mut buffer_len = out.len() + addr_align as usize;
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let buf_align = buffer_len & (BUF_LEN_ALIGN - 1);
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if buf_align > 0 {
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buffer_len += BUF_LEN_ALIGN - buf_align;
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}
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buffer_len = buffer_len.max(BUF_MIN_LEN);
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// note that this always holds true because addr alignment is equal to buf length alignment
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assert!(buffer_len >= out.len());
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// we never want to cross page boundaries, otherwise the read will just not work
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assert_eq!(
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page_addr.to_umem() - (page_addr.to_umem() & (PAGE_SIZE as umem - 1)),
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(page_addr_align + buffer_len as umem - 1)
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- ((page_addr_align + buffer_len as umem - 1)
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& (PAGE_SIZE as umem - 1))
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);
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let buffer = vec![0u8; buffer_len].into_boxed_slice();
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let buffer_ptr = Box::into_raw(buffer) as *mut u8;
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@ -179,8 +198,8 @@ impl PhysicalMemory for PciLeech {
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out_end: out.len() + addr_align as usize,
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});
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unsafe { (*mem).qwA = page_addr.as_u64() - addr_align };
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unsafe { (*mem).pb = buffer_ptr };
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unsafe { (*mem).qwA = page_addr_align };
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unsafe { (*mem).__bindgen_anon_1.pb = buffer_ptr };
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unsafe { (*mem).cb = buffer_len as u32 };
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}
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@ -223,12 +242,24 @@ impl PhysicalMemory for PciLeech {
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Ok(())
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}
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fn phys_write_raw_list(&mut self, data: &[PhysicalWriteData]) -> Result<()> {
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//let mem_map = &self.mem_map;
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fn phys_write_raw_iter<'a>(
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&mut self,
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data: CIterator<PhysicalWriteData<'a>>,
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out_fail: &mut WriteFailCallback<'_, 'a>,
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) -> Result<()> {
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let vec = if let Some(mem_map) = &self.mem_map {
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mem_map
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.map_iter(data, out_fail)
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.map(|d| (d.0 .0.into(), d.1))
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.collect::<Vec<_>>()
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} else {
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data.map(|MemData(addr, buf)| (addr, buf))
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.collect::<Vec<_>>()
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};
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// get total number of pages
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let num_pages = data.iter().fold(0u64, |acc, read| {
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acc + calc_num_pages(read.0.as_u64(), read.1.len() as u64)
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let num_pages = vec.iter().fold(0u64, |acc, read| {
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acc + calc_num_pages(read.0.to_umem(), read.1.len() as u64)
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});
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// allocate scatter buffer
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@ -242,37 +273,53 @@ impl PhysicalMemory for PciLeech {
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)
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};
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if result != 1 {
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return Err(Error::Connector("unable to allocate scatter buffer"));
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return Err(Error(ErrorOrigin::Connector, ErrorKind::InvalidMemorySize)
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.log_error("unable to allocate scatter buffer"));
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}
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// prepare mems
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let mut gaps = Vec::new();
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let mut i = 0usize;
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for write in data.iter() {
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for write in vec.iter() {
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for (page_addr, out) in write.1.page_chunks(write.0.into(), PAGE_SIZE) {
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let mem = unsafe { *mems.add(i) };
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let addr_align = page_addr.as_u64() & (BUF_ALIGN - 1);
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let addr_align = page_addr.to_umem() & (BUF_ALIGN - 1);
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let len_align = out.len() & (BUF_LEN_ALIGN - 1);
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if addr_align == 0 && len_align == 0 && out.len() >= BUF_MIN_LEN {
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// properly aligned read
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unsafe { (*mem).qwA = page_addr.as_u64() };
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unsafe { (*mem).pb = out.as_ptr() as *mut u8 };
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// properly aligned write
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unsafe { (*mem).qwA = page_addr.to_umem() };
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unsafe { (*mem).__bindgen_anon_1.pb = out.as_ptr() as *mut u8 };
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unsafe { (*mem).cb = out.len() as u32 };
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} else {
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// non-aligned or small read
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let mut buffer_len = (out.len() + addr_align as usize).max(BUF_MIN_LEN);
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buffer_len += BUF_LEN_ALIGN - (buffer_len & (BUF_LEN_ALIGN - 1));
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// prepare gap buffer for reading
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let write_addr = (page_addr.as_u64() - addr_align).into();
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// non-aligned or small write
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let page_addr_align = page_addr.to_umem() - addr_align;
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let mut buffer_len = out.len() + addr_align as usize;
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let buf_align = buffer_len & (BUF_LEN_ALIGN - 1);
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if buf_align > 0 {
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buffer_len += BUF_LEN_ALIGN - buf_align;
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}
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buffer_len = buffer_len.max(BUF_MIN_LEN);
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// note that this always holds true because addr alignment is equal to buf length alignment
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assert!(buffer_len >= out.len());
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// we never want to cross page boundaries, otherwise the write will just not work
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assert_eq!(
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page_addr.to_umem() - (page_addr.to_umem() & (PAGE_SIZE as umem - 1)),
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(page_addr_align + buffer_len as umem - 1)
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- ((page_addr_align + buffer_len as umem - 1)
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& (PAGE_SIZE as umem - 1))
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);
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// prepare gap buffer for writing
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let buffer = vec![0u8; buffer_len].into_boxed_slice();
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let buffer_ptr = Box::into_raw(buffer) as *mut u8;
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// send over to our gaps list
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gaps.push(WriteGap {
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gap_addr: write_addr,
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gap_addr: page_addr_align.into(),
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gap_buffer: buffer_ptr,
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gap_buffer_len: buffer_len,
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in_buffer: out.as_ptr(),
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@ -281,8 +328,8 @@ impl PhysicalMemory for PciLeech {
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});
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// store pointers into pcileech struct for writing (after we dispatched a read)
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unsafe { (*mem).qwA = write_addr.as_u64() };
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unsafe { (*mem).pb = buffer_ptr };
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unsafe { (*mem).qwA = page_addr_align };
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unsafe { (*mem).__bindgen_anon_1.pb = buffer_ptr };
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unsafe { (*mem).cb = buffer_len as u32 };
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}
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@ -292,18 +339,25 @@ impl PhysicalMemory for PciLeech {
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// dispatch necessary reads to fill the gaps
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if !gaps.is_empty() {
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let mut datas = gaps
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let mut vec = gaps
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.iter()
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.map(|g| {
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PhysicalReadData(g.gap_addr, unsafe {
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slice::from_raw_parts_mut(g.gap_buffer, g.gap_buffer_len)
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})
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MemData(
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g.gap_addr,
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unsafe { slice::from_raw_parts_mut(g.gap_buffer, g.gap_buffer_len) }.into(),
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)
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})
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.collect::<Vec<_>>();
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self.phys_read_raw_list(datas.as_mut_slice())?;
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let mut iter = vec
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.iter_mut()
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.map(|MemData(a, d): &mut PhysicalReadData| MemData(*a, d.into()));
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for (gap, read) in gaps.iter().zip(datas) {
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let out_fail = &mut |_| true;
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self.phys_read_raw_iter((&mut iter).into(), &mut out_fail.into())?;
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for (gap, mut read) in gaps.iter().zip(vec) {
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let in_buffer =
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unsafe { slice::from_raw_parts(gap.in_buffer, gap.in_end - gap.in_start) };
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read.1[gap.in_start..gap.in_end].copy_from_slice(in_buffer);
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@ -334,21 +388,89 @@ impl PhysicalMemory for PciLeech {
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}
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fn metadata(&self) -> PhysicalMemoryMetadata {
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self.metadata
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let (max_address, real_size) = if let Some(mem_map) = &self.mem_map {
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(mem_map.max_address(), mem_map.real_size())
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} else {
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(
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(self.conf.paMax as usize - 1_usize).into(),
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self.conf.paMax as umem,
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)
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};
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PhysicalMemoryMetadata {
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max_address,
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real_size,
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readonly: self.conf.fVolatile == 0,
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ideal_batch_size: 128,
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}
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}
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// Sets the memory map only in cases where no previous memory map was being set by the end-user.
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fn set_mem_map(&mut self, mem_map: &[PhysicalMemoryMapping]) {
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if self.mem_map.is_none() {
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self.mem_map = Some(MemoryMap::<(Address, umem)>::from_vec(mem_map.to_vec()));
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}
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}
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}
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fn validator() -> ArgsValidator {
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|
ArgsValidator::new()
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|
.arg(ArgDescriptor::new("default").description("the target device to be used by LeechCore"))
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|
.arg(ArgDescriptor::new("device").description("the target device to be used by LeechCore"))
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.arg(ArgDescriptor::new("memmap").description("the memory map file of the target machine"))
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}
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|
/// Creates a new PciLeech Connector instance.
|
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|
|
|
#[connector(name = "pcileech")]
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|
|
|
#[connector(name = "pcileech", help_fn = "help", target_list_fn = "target_list")]
|
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|
|
|
pub fn create_connector(args: &ConnectorArgs) -> Result<PciLeech> {
|
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|
|
|
let device = args
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|
|
.get("device")
|
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|
|
.or_else(|| args.get_default())
|
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|
.ok_or(Error::Connector("argument 'device' missing"))?;
|
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|
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|
|
if let Some(memmap) = args.get("memmap") {
|
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|
|
|
PciLeech::with_memmap(device, memmap)
|
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|
|
} else {
|
|
|
|
|
PciLeech::new(device)
|
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|
|
|
let validator = validator();
|
|
|
|
|
|
|
|
|
|
let args = &args.extra_args;
|
|
|
|
|
|
|
|
|
|
match validator.validate(args) {
|
|
|
|
|
Ok(_) => {
|
|
|
|
|
let device = args
|
|
|
|
|
.get("device")
|
|
|
|
|
.or_else(|| args.get_default())
|
|
|
|
|
.ok_or_else(|| {
|
|
|
|
|
Error(ErrorOrigin::Connector, ErrorKind::ArgValidation)
|
|
|
|
|
.log_error("'device' argument is missing")
|
|
|
|
|
})?;
|
|
|
|
|
|
|
|
|
|
if let Some(memmap) = args.get("memmap") {
|
|
|
|
|
PciLeech::with_mem_map_file(device, memmap)
|
|
|
|
|
} else {
|
|
|
|
|
PciLeech::new(device)
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
Err(err) => {
|
|
|
|
|
error!(
|
|
|
|
|
"unable to validate provided arguments, valid arguments are:\n{}",
|
|
|
|
|
validator
|
|
|
|
|
);
|
|
|
|
|
Err(err)
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// Retrieve the help text for the Qemu Procfs Connector.
|
|
|
|
|
pub fn help() -> String {
|
|
|
|
|
let validator = validator();
|
|
|
|
|
format!(
|
|
|
|
|
"\
|
|
|
|
|
The `pcileech` connector implements the LeechCore interface of pcileech for memflow.
|
|
|
|
|
|
|
|
|
|
More information about pcileech can be found under https://github.com/ufrisk/pcileech.
|
|
|
|
|
|
|
|
|
|
This connector requires access to the usb ports to access the pcileech hardware.
|
|
|
|
|
|
|
|
|
|
Available arguments are:
|
|
|
|
|
{}",
|
|
|
|
|
validator.to_string()
|
|
|
|
|
)
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// Retrieve a list of all currently available PciLeech targets.
|
|
|
|
|
pub fn target_list() -> Result<Vec<TargetInfo>> {
|
|
|
|
|
// TODO: check if usb is connected, then list 1 target
|
|
|
|
|
Ok(vec![])
|
|
|
|
|
}
|
|
|
|
|
|
ko1N
3 years ago
committed by
GitHub